Programmable Phase Frequency Divider With SEU-Hardened CMOS Flip-Flops
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Solution Overview
Problem
CMOS circuits in space applications are vulnerable to single event upsets (SEUs) due to radiation exposure, particularly at high frequencies where the timing window for set and hold of flip flops is consistently covered by SEU hits, leading to potential soft errors.
Innovation Solution
A radiation hardened programmable phase frequency divider design utilizing dual master and slave latch circuits with complementary data inputs and outputs, implemented in deep submicron CMOS technology, which connects clock and data inputs in parallel and cross-connects data outputs as feedback inputs to mitigate the effects of SEUs, ensuring operation immunity to single event upsets at GHz frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a PPFD is fabricated in deep submicron technology to operate at GHz frequencies, then operating speed is improved, but vulnerability to SEU increases because the timing window is always covered by SEU hits
Solution Approach 1:
The flip-flop is divided into two separate half circuits, each processing one pair of complementary inputs. This segmentation allows the circuit to tolerate SEUs in one half while the other half remains functional, resolving the contradiction between high-speed operation and SEU immunity.
Solution Approach 2:
The patent introduces asymmetric error detection logic that monitors for impossible transitions (such as both Q and Q_bar changing simultaneously). This asymmetric monitoring approach enables the high-speed circuit to detect and correct SEUs that occur during the critical timing window, maintaining reliability at GHz frequencies.
2Reliability
If a dual interlocked cell (DICE) type flip flop design is used to protect against SEU, then reliability is improved, but the circuit cannot operate at GHz frequencies because the vulnerable timing window is always covered by SEU hits
Solution Approach 1:
By segmenting the flip-flop into two independent half circuits with separate error detection paths, the design achieves DICE-level reliability without the speed penalties. Each half can be optimized for high-speed operation while the combined structure provides redundant error protection.
Solution Approach 2:
The patent changes the error detection parameter from monitoring individual node transitions to monitoring complementary pairs simultaneously. This parameter change enables detection of SEUs at GHz speeds by looking for impossible state transitions rather than relying on slower timing-based detection methods.
3Reliability
If four complementary data inputs are used in the master latch, then error detection capability is improved, but device complexity increases
Solution Approach 1:
The patent merges the error detection function into the existing latch structure by using the same four complementary inputs for both data storage and error detection. This combining approach provides enhanced error detection capability without adding separate complexity, as the dual half-circuit structure naturally provides the redundancy needed for error detection.
Data Source
AI summary
The present invention provides a programmable phase frequency divider circuit implemented in CMOS technology for space applications. The programmable phase frequency divider consists of three radiation hardened D-type flip flops and combinational logic circuits to provide the feedback controls that allow programmable frequency division ratios from 1 to 8. The radiation hardened D-type flip flop circuits are designed to keep on running properly at GHz frequencies even after a single event upset (SEU) hit. The novel D-type flip flop circuits each have two pairs of complementary inputs and outputs to mitigate SEU's. The combinational logic circuits are designed to utilize the complementary outputs in such a way that only one of the four dual complementary inputs to any D-type flip flop gets flipped at most after an SEU hit.