Phase Interpolation Circuit Clock Switching Without Glitches
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Solution Overview
Problem
Phase-interpolating circuits face glitches during clock switching due to improper timing, requiring complex sequential control circuits that increase design complexity and power consumption.
Innovation Solution
A method involving a reference signal, generation of phase signals, and a state machine to selectively input these signals into the phase-interpolating circuit based on logic high or low conditions, allowing for glitch-free switching without sequential control, using a multiplexer and delay-locked loop to manage phase interpolation ratios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional sequential control circuits are used to ensure clock switching occurs at logic low, then glitches are prevented, but circuit design complexity and power consumption increase
Solution Approach 1:
The patent extracts and removes the complex sequential control circuit from the phase-interpolating system. Instead of using traditional enable signals with sequential control to manage clock switching, the invention directly switches between clock inputs based on phase rotation values, eliminating the source of complexity while maintaining glitch-free operation through a different mechanism.
Solution Approach 2:
The patent segments the phase-interpolating circuit into distinct functional blocks: a phase rotation value generation unit and a phase interpolation unit. This segmentation allows independent optimization of each block, enabling the removal of sequential control from the overall system while maintaining reliable glitch-free switching through the specific architecture of the segmented components.
2Stability of the object's composition
If complex sequential control circuits are implemented to manage clock switching timing, then output phase stability is improved, but design difficulty increases
Solution Approach 1:
The patent introduces a phase rotation value as an intermediary parameter that mediates between the desired output phase and the actual clock switching operation. This intermediary allows the system to achieve stable phase output without requiring complex sequential control circuits, as the phase rotation value directly controls the interpolation ratio in a straightforward manner.
Solution Approach 2:
The patent changes the control parameter from complex sequential enable signals to a simple phase rotation value that directly determines the interpolation ratio. This parameter change simplifies the design process while maintaining output phase stability, as the phase rotation value can be calculated and applied without complex timing control.
3Device complexity
If clock switching is performed without proper sequential control, then circuit complexity is reduced, but glitches occur during switching
Solution Approach 1:
The patent performs preliminary calculation of the phase rotation value before the actual clock switching occurs. By pre-determining the interpolation ratio based on the desired output phase, the system ensures that clock switching happens at the optimal moment without requiring complex sequential control, thereby preventing glitches while maintaining simple circuitry.
Solution Approach 2:
The patent replaces the mechanical sequential control system with a direct digital control approach. Instead of using enable signals and sequential logic to manage clock switching, the invention uses a phase rotation value to directly control the interpolation operation, substituting a simpler digital mechanism for the complex sequential control system and eliminating glitches in the process.
Data Source
AI summary
The present invention relates to a method and an apparatus, during a phase switching process, for choosing all of outputted phases upon the clock phases devoid of phase switching so as to avoid glitches during clock switching. Compared with the conventional approach for removing glitches by controlling a clock switching sequence, an improvement of a phase rotator is further disclosed in the present invention, which eliminates the glitches of the outputted phase clock so as to realize a glitch-less phase switching in a phase interpolation circuit.