Phase Interpolator Circuit for Linear Low-Noise Clock Interpolation
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Solution Overview
Problem
Existing phase interpolators face challenges in achieving good linearity and low noise performance, particularly due to the dependency on the match between components in constant slope interpolating circuit units.
Innovation Solution
A phase interpolator design that utilizes a circuit unit with a capacitor and resistors in parallel, where connecting switches are operated based on input clocks to control charging and discharging, allowing for improved linearity and noise performance through controlled voltage development across the capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If constant slope interpolating circuit units are used, then good linearity of the interpolating operation is achieved, but noise performance deteriorates and component matching requirements increase
Solution Approach 1:
The patent replaces the traditional constant slope charging circuit (which uses current sources and switches) with a relaxation oscillator-based circuit. This substitution eliminates the need for precise component matching and reduces noise by using a different operating principle - charging a capacitor through a resistor until a threshold voltage is reached, which inherently provides better noise performance while maintaining good linearity.
2Manufacturing precision
If constant slope interpolating circuit units are used, then good linearity of the interpolating operation is achieved, but device complexity increases due to stringent component matching requirements
Solution Approach 1:
The patent replaces the traditional constant slope interpolating circuit with a relaxation oscillator circuit that charges a capacitor through a resistor. This substitution eliminates the need for precise matching of current sources and switches, thereby reducing device complexity and manufacturing difficulty while maintaining good linearity performance.
Solution Approach 2:
The relaxation oscillator circuit is self-regulating - the capacitor charges automatically through the resistor until it reaches the threshold voltage, at which point the inverter output switches and discharges the capacitor. This self-service mechanism eliminates the need for complex external control circuits and precise component matching, simplifying the overall device structure.
3Device complexity
If simple interpolating circuit units are used, then device complexity is reduced, but linearity and noise performance deteriorate
Solution Approach 1:
The patent replaces complex constant slope charging circuits with simpler relaxation oscillator circuits. The simplified circuit uses basic components (resistor, capacitor, inverter) arranged in a feedback configuration that inherently provides both good linearity and low noise performance, achieving circuit simplicity without sacrificing performance.
Solution Approach 2:
The patent introduces feedback by connecting the inverter output back to the switch that controls capacitor charging. This feedback mechanism ensures that the capacitor charges and discharges in a controlled manner, maintaining good linearity and noise performance while keeping the circuit structure simple and easy to implement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves improved linearity and reduced noise in the phase interpolation process by effectively managing the voltage across the capacitor, enabling the generation of an output clock with an interpolated phase between the input clock phases.
Implementation Method 1
a capacitor and a plurality of resistors in parallel, where the resistors are connected between a first supply line for receiving a first DC potential and a second supply line for receiving a second DC potential
Implementation Method 2
a circuit unit with a capacitor and resistors in parallel, where the resistors are connected between a first supply line for receiving a first DC potential and a second supply line for receiving a second DC potential
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
A phase interpolator (100) to receive a first and a second input clock (110, 120) with a first and a second input clock edge (111, 121) comprises an interpolating circuit unit comprising: resistors (153a, 153b) in parallel; for each resistor (153a, 153b), a connecting switch (157a, 157b) to connect and disconnect, as operated in accordance with one of the first and the second input clocks (110, 120), the resistor (157a, 157b) to and from a first supply line; and a capacitor (161) in series with the resistors (153a, 153b). The phase interpolator (100) allow controlling a partial group of the connecting switches (157a) to be operated in accordance with the first input clock (110), and controlling the rest of the connecting switches (157b) to be operated in accordance with the second input clock (120); and determine the output clock (130) of the phase interpolator (100) on the basis of an output signal (170) of the interpolating circuit unit (150), defined by the voltage over the capacitor (161) after the second input clock edge (121).