Phase Interpolator Calibration Circuit for Clock Linearity
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Solution Overview
Problem
Existing electronic systems face challenges in maintaining linearity due to deviations from ideal behavior caused by deterministic and random sources, leading to non-linearities that affect phase interpolators and clock data recovery circuits, limiting their performance and accuracy.
Innovation Solution
A calibration circuit incorporating a multi-phase clock generator, pre-skew buffer, phase interpolator, and phase detection circuit to adjust non-linearity by generating and fine-tuning multi-phase clock signals, using injection-locked oscillators, current digital-to-analog converters, and voltage-to-current converters to minimize phase errors and skew.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a phase interpolator is used to generate phase-shifted clock signals, then the system can achieve flexible phase control, but non-linearity in the phase interpolation process degrades measurement precision and system accuracy
Solution Approach 1:
The patent applies preliminary action by performing calibration measurements before actual operation. The system pre-determines calibration codes that compensate for non-linearity in the phase interpolator, storing these correction values for later use during normal operation, thereby improving phase measurement accuracy without affecting real-time performance
Solution Approach 2:
The patent implements feedback by using a phase detection circuit to measure the actual phase output of the interpolator and compare it with the ideal linear response. This feedback information is used to generate calibration codes that correct the non-linearity, creating a closed-loop system that continuously compensates for deviations
2Measurement precision
If calibration circuits and phase detection circuits are added to correct non-linearity, then measurement precision improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the calibration function into separate dedicated circuits: a phase detection circuit for measuring non-linearity, a calibration code generation unit for computing corrections, and a lookup table for storing calibration data. This modular approach allows precise calibration while keeping each component's complexity manageable and reusable
Solution Approach 2:
The system performs self-calibration by automatically detecting its own non-linearity characteristics through the phase detection circuit and generating appropriate calibration codes without requiring external intervention or manual adjustment, thereby improving accuracy while minimizing the operational complexity for users
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The calibration circuit significantly reduces non-linearities in phase interpolators, enhancing the accuracy and precision of clock data recovery, allowing systems to meet stringent performance requirements by correcting phase errors and improving signal-to-noise ratio.
Implementation Method 1
the multi-phase clock generator including a first injection-locked oscillator
Data Source
AI summary
Embodiments herein describe a calibration circuit including a multi-phase clock generator configured to receive a clock signal and generate a multi-phase clock output, the multi-phase clock generator including a first injection-locked oscillator, a mixer, a current digital-to-analog converter (IDAC), and a voltage to current converter (VTOI), the IDAC and VTOI configured to fine tune offsets of the mixer and an input of the VTOI, and overcome phase errors from injection locking disturbance. The multi-phase clock generator further includes a pre-skew buffer configured to receive the multi-phase clock output from the multi-phase clock generator and generate multiple data signals and a phase interpolator (PI) configured to receive the multiple data signals from the pre-skew buffer and generate a shifted clock signal of the clock signal received by the multi-phase clock generator.