Phase Interpolator Cell Switching to Eliminate Crossbar Current

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Solution Overview

Problem

Phase interpolator circuits experience non-linearity and jitter due to crossbar current caused by simultaneous operation of pull-up and pull-down networks, which reduces the speed of the phase interpolator.

Innovation Solution

A phase interpolator cell design that includes multiplexers to selectively enable either the first or second pull-up and pull-down networks based on clock signals, preventing simultaneous connection to power supplies and thus eliminating crossbar current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple pull-up networks and pull-down networks are connected to the same output node simultaneously, then the phase interpolator can process multiple clock signals, but crossbar current is generated causing non-linearity and jitter

Engineering Contradiction:

Improveability to process multiple clock signalsVSAvoidoutput signal quality

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The pull-up networks and pull-down networks are segmented into separate groups, each associated with a specific clock signal. The multiplexer selectively connects only the relevant pull-up and pull-down networks to the output node based on which clock signal is currently being processed, preventing simultaneous operation of conflicting networks and eliminating crossbar current.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The connection between the pull-up/pull-down networks and the output node is made dynamic through the multiplexer. The multiplexer dynamically switches which networks are connected to the output node based on the current operation phase, allowing the system to adaptively prevent crossbar current while maintaining the ability to process multiple clock signals.

Inventive Principle:

Principle #15Dynamics

2Duration of action of moving object

If multiple pull-up and pull-down networks operate simultaneously, then the phase interpolator can maintain continuous clock signal processing, but the speed of the phase interpolator is reduced due to crossbar current

Engineering Contradiction:

Improvecontinuous clock signal processingVSAvoidphase interpolator speed

Core Design Contradiction:

Duration of action of moving objectVSSpeed

Solution Approach 1:

The operation is divided into periodic phases where different sets of pull-up and pull-down networks are activated in sequence rather than simultaneously. The multiplexer switches between different network configurations in a periodic manner corresponding to the clock signal phases, eliminating crossbar current while maintaining continuous processing capability.

Inventive Principle:

Principle #19Periodic action

3Ease of operation

If pull-up and pull-down networks are turned on at the same time, then the circuit can respond to both clock signals, but non-linearity and jitter are introduced to the output clock signal

Engineering Contradiction:

Improveresponse to multiple clock signalsVSAvoidoutput clock signal accuracy

Core Design Contradiction:

Ease of operationVSManufacturing precision

Solution Approach 1:

The problematic simultaneous operation of pull-up and pull-down networks is extracted and eliminated from the system. The multiplexer configuration ensures that only one set of pull-up and pull-down networks is active at any given time, removing the source of crossbar current and its associated non-linearity and jitter from the output signal.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS11218140B1Cross-phase detector based phase interpolator

Publication Date: 2022.01.04 APPLE INC

AI summary

Embodiments relate to a phase interpolator cell. The phase interpolator cell includes a multiplexer configured to select between a first pull-up network and a second pull-up network. The first pull-up network includes a first pull-up transistor controlled by a first clock signal and is connected between a first input of the multiplexer and a first power supply. The second pull-up network includes a second pull-up transistor controlled by a second clock signal and is connected between a second input of the multiplexer and the first power supply.