Digital Phase Interpolator Precharge Circuit for Low-Jitter Linearity
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Solution Overview
Problem
Conventional phase interpolators suffer from non-linearity and increased jitter due to parasitic capacitances and memory effects, which affect the accuracy of fractional dividers and other circuits relying on clock phase synthesis.
Innovation Solution
The implementation of precharge transistors driven by inverse clock signals to precharge intermediate nodes, ensuring that voltages at these nodes are independent of previous control words, and the use of weighted switches with proportional capacitance to control the discharge time, thereby maintaining linear phase interpolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional phase interpolators are used to generate fractional frequencies, then frequency synthesis is achieved, but spurs and jitter are introduced
Solution Approach 1:
The patent applies preliminary action by precharging intermediate nodes to a predetermined voltage level before the actual phase interpolation operation. This precharging step, performed in advance through precharge transistors, ensures that nodes start from a known state, eliminating memory effects and reducing jitter without affecting the frequency synthesis capability
Solution Approach 2:
The phase interpolator circuit is segmented into distinct functional blocks: precharge transistors for node initialization, control switches for phase selection, and weighted switches for fractional control. This segmentation isolates the precharging function from the interpolation function, allowing independent optimization of each to reduce spurs and jitter while maintaining frequency accuracy
2Ease of manufacture
If parasitic capacitances are present in the phase interpolator, then circuit implementation is simplified, but non-linearity and memory effects increase
Solution Approach 1:
The patent extracts the harmful effect of parasitic capacitances by introducing precharge transistors that actively reset intermediate nodes to a known voltage state. This extraction removes the memory effect caused by parasitic capacitances accumulating charge, thereby eliminating non-linearity while keeping the overall circuit structure simple and manufacturable
3Device complexity
If intermediate nodes are not precharged, then device complexity is reduced, but output phase linearity deteriorates
Solution Approach 1:
The precharge transistors act as intermediary elements between the power supply and the intermediate nodes. These intermediaries actively manage the voltage state of nodes, ensuring linear phase output by preventing charge accumulation from parasitic capacitances, while adding minimal complexity to the overall circuit
Data Source
AI summary
An apparatus comprising: a first control switch driven by a first bit value; a first weighted switch driven by a first clock signal; a first intermediate node coupled between the first control switch and the second weighted switch; a first precharge transistor coupled to the first intermediate node, wherein the precharge transistor is driven by an inverse of the clock signal; a second control switch driven by an inverse of the bit; a second weighted switch driven by a second clock signal; a second intermediate node coupled between the second control switch and the second weighted switch; a second precharge transistor coupled to the second intermediate node, wherein the second precharge transistor is driven by an inverse of the second clock signal; and a capacitor coupled to the first control switch, the second control switch, the first precharge transistor and the second precharge transistor.