Phase Interpolator Input Control for Glitch-Free Clock Switching
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Solution Overview
Problem
Conventional phase interpolators in integrated circuits experience glitches and false frequency lock due to asynchronous updates of phase selection codes at high frequencies, which are sensitive to device corner, supply voltage, temperature, and clock frequency, leading to inaccurate frequency counting.
Innovation Solution
An input controller generates a delayed phase interpolator code with a known phase relationship to the input clock, ensuring zero glitches by adding a variable delay to the phase selection code to switch only in safe zones, determined by sensing the time spacing between the code and input clock phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If phase selection code is updated asynchronously at high frequencies, then frequency tracking capability is improved, but glitches and false frequency lock occur
Solution Approach 1:
The patent applies preliminary action by determining the safe zone window before updating the phase selection code. The controller identifies a time window where all input clock phases are at the same logic level (safe zone) and schedules the code update to occur within this pre-determined window, preventing glitches while maintaining high-frequency operation
Solution Approach 2:
The patent uses feedback by continuously monitoring the logic levels of multiple input clock phases to dynamically identify the safe zone window. The controller adjusts the timing of phase selection code updates based on real-time feedback about clock phase states, ensuring updates only occur when safe zones are detected
2Measurement precision
If phase selection code update timing is extended, then safe zone detection accuracy is improved, but update window opportunity decreases
Solution Approach 1:
The patent maintains continuity of useful action by continuously monitoring clock phase logic levels without interruption. The controller keeps track of safe zone windows across multiple clock cycles, ensuring that code updates can be performed promptly when safe zones occur, maximizing update opportunities while maintaining detection accuracy
3Speed
If phase selection code is updated during unsafe zone, then update speed is improved, but output clock phase produces glitches
Solution Approach 1:
The patent applies preliminary anti-action by proactively preventing code updates during unsafe zones where clock phases are transitioning. The controller identifies unsafe zones in advance and blocks updates during these periods, eliminating the harmful effect of glitches before they can occur at the output
Data Source
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AI summary
An integrated circuit device includes a sensing circuit configured to determine a delay code from a plurality of delay codes using a phase interpolation (PI) code and a plurality of input clock phases, a variable delay circuit coupled to the sensing circuit and configured to generate a variable delay based on the delay code and generate a delayed PI code using the PI code and the delay code, the delayed PI code corresponding to a code obtained from adding the variable delay to the PI code, and a phase interpolator coupled to the variable delay circuit and configured to generate an output clock phase from the plurality of input clock phases using the delayed PI code.