Phase Interpolator Calibration Using Amplified Timing Differences
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Solution Overview
Problem
Phase interpolators suffer from nonlinearity due to device/layout mismatches, leading to poor clock performance and increased bit error rates.
Innovation Solution
A time amplifier-based clock phase calibration circuit that uses capacitive load stages with proportional or fixed capacitances to calibrate phase interpolators, adjusting the time intervals of capacitor charging and discharging to achieve precise phase alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If phase interpolation is used to generate fine clock phases, then clock phase resolution is improved, but nonlinearity increases due to device/layout mismatch
Solution Approach 1:
The patent applies preliminary action by pre-calibrating the phase interpolator before normal operation. A calibration circuit measures the actual phase differences between clock signals and stores correction values in a lookup table. During operation, these pre-computed correction values are applied to compensate for nonlinearity, thereby maintaining both fine phase resolution and phase linearity without requiring complex real-time correction mechanisms.
2Measurement precision
If calibration circuits are added to correct phase nonlinearity, then phase accuracy is improved, but device complexity increases
Solution Approach 1:
The patent uses copying by creating a separate calibration circuit that replicates the phase interpolation function but operates independently to measure and characterize nonlinearity. The calibration circuit generates correction values that are stored in a lookup table, which is then copied and applied during normal operation. This approach achieves high phase accuracy without significantly increasing the complexity of the main phase interpolator circuit.
3Measurement precision
If time amplifier is used to amplify timing differences, then measurement sensitivity is improved, but noise increases
Solution Approach 1:
The patent applies periodic action by using periodic calibration sequences where the time amplifier measures timing differences at multiple discrete phase points throughout the clock cycle. By periodically sampling at optimized intervals and averaging the results, the system achieves high measurement sensitivity while the periodic nature allows for noise correlation techniques that distinguish signal from random noise, thereby reducing the impact of noise amplification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces integrated and differential nonlinearity, improving phase accuracy and reducing noise, spurious tones, and phase accuracy in clock generation circuits.
Implementation Method 1
A time amplifier-based clock phase calibration circuit that uses capacitive load stages with proportional or fixed capacitances to calibrate phase interpolators
Data Source
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AI summary
Systems and methods related to calibrating a phase interpolator by amplifying timing differences are described. An example system includes a calibration stage configured to output a calibration code for a phase interpolator. The system further includes control logic configured to: (1) at least partially discharge a first pre-charged capacitive load in response to a signal output by the phase interpolator based on the calibration code, and (2) at least partially discharge a second pre-charged capacitive load in response to a reference signal associated with the phase interpolator. The system further includes a feedback path configured to provide feedback to the calibration stage to allow for a modification of the calibration code, where the feedback is dependent on a first voltage provided by the first pre-charged capacitive load and a second voltage provided by the second pre-charged capacitive load.