Phase-Lock Assistant Circuit for Variable-Frequency CDR Locking
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Solution Overview
Problem
In phase-lock-loop based clock-data recovery (PLL-based CDR) circuitry, the voltage-controlled oscillator (VCO) fails to lock into the input data when the input frequency varies, leading to a deviation between the frequency of the input data and the reference clock, which affects the phase lock between the input data and the VCO output.
Innovation Solution
A phase-lock assistant circuit is introduced to align the input data and the VCO output by generating multiple phase clocks and using a phase frequency detector and phase detector to adjust the frequency of the VCO, ensuring the data edge is aligned with the rising edge of the clock, and a charge pump is used to drive a low pass filter to adjust the frequency accordingly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a two-loop PLL structure is used to bring VCO frequency closer to input data frequency, then frequency alignment is improved, but phase locking reliability deteriorates when input frequency varies during transition
Solution Approach 1:
The patent applies preliminary action by detecting frequency variation during the transition from first loop to second loop before phase locking can fail. The frequency variation detector identifies when input frequency changes, and the phase lock assistant circuit proactively adjusts the VCO frequency in advance to prevent loss of lock, rather than waiting for the locking failure to occur.
Solution Approach 2:
The patent implements feedback by continuously monitoring the frequency relationship between input data and VCO output during loop transition. The frequency variation detector provides real-time feedback about frequency changes, which the phase lock assistant circuit uses to dynamically adjust the VCO frequency, creating a closed-loop control system that maintains reliable phase locking despite frequency variations.
2Measurement precision
If spread spectrum clock is used in two-loop structure, then clock signal quality is improved, but VCO locking capability deteriorates when input frequency varies
Solution Approach 1:
The patent introduces an intermediary element - the phase lock assistant circuit - that mediates between the spread spectrum clock signal and the VCO during frequency transitions. This intermediary detects frequency variations and provides corrective frequency adjustments to the VCO, enabling the system to maintain locking capability while still benefiting from the improved clock signal quality provided by spread spectrum modulation.
3Measurement precision
If phase frequency detector and charge pump are used to adjust VCO frequency, then phase alignment is improved, but circuit complexity increases
Solution Approach 1:
The patent applies universality by designing the phase lock assistant circuit to perform multiple functions: it detects frequency variations, determines whether to adjust VCO frequency up or down, generates appropriate adjustment signals, and coordinates with the phase frequency detector and charge pump. This multi-functional approach consolidates several operations into a single integrated circuit block, improving phase alignment capability while limiting the increase in overall circuit complexity.
Data Source
AI summary
A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.