Phase-Rotator Fractional-N PLL for Wideband Low-Noise Locking
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Solution Overview
Problem
Fractional-N phase locked loops face limitations in achieving low total noise over a broad bandwidth due to high-frequency delta-sigma noise, and they struggle with narrow frequency locking ranges and poor noise characteristics, especially in high-speed communication and sensor systems.
Innovation Solution
A fractional-N sub-sampling phase locked loop using a phase rotator, which includes a frequency locked loop locked at a fractional-N frequency via a first delta-sigma modulator and a sub-sampling phase locked loop that locks phase using a phase rotator, applying a fractional multiple to the signal output from the oscillator, thereby reducing delta-sigma noise and enhancing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a general fractional-N phase locked loop uses a delta-sigma modulator to randomly shake a divider value, then fractional multiple frequency can be generated, but high-frequency delta-sigma noise is generated which limits total noise performance over broad bandwidth
Solution Approach 1:
The patent divides the single fractional-N PLL into two separate loops: an integer-N frequency locked loop and a sub-sampling phase locked loop. The delta-sigma modulator is only used in the frequency locked loop for coarse frequency adjustment, while the phase locked loop uses integer division ratios, eliminating the source of delta-sigma noise from the phase detection path.
Solution Approach 2:
The harmful delta-sigma noise generation is extracted and isolated to only the frequency locked loop portion, while the phase locked loop uses a clean integer-N division path. This separates the noise-generating function from the phase detection function.
2Speed
If the phase locked loop uses a broad bandwidth to increase operation speed, then operation speed improves, but noise performance deteriorates due to delta-sigma noise
Solution Approach 1:
The system separates frequency control and phase control into independent loops with different bandwidth characteristics. The frequency locked loop handles coarse frequency adjustment, while the phase locked loop with integer-N division provides clean phase detection with broad bandwidth capability without being contaminated by delta-sigma noise.
3Speed
If a sub-sampling phase locked loop samples a fast oscillator output signal into a slow input signal, then bandwidth can be increased, but phase noise characteristics deteriorate
Solution Approach 1:
The patent applies different quality characteristics to different parts of the system: the frequency locked loop uses delta-sigma modulation for frequency control, while the phase locked loop uses clean integer-N division for phase control. This local differentiation ensures that phase noise is not degraded by delta-sigma noise in the critical phase detection path.
Data Source
AI summary
According to an exemplary embodiment of the present disclosure, a fractional-N sub-sampling phase locked loop using a phase rotator includes a frequency locked loop which is locked at a fractional-N frequency using a delta-signal modulator and a sub-sampling phase locked loop which locks a phase to a fractional multiple using a phase rotator, and the phase rotator applies a fractional multiple to a phase of a signal output from the oscillator.