Phased LPN Bitmap Generation for DRAMLess SSD Garbage Collection
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Solution Overview
Problem
Solid-State Drives (SSDs) without Dynamic Random-Access Memory (DRAM) face challenges in meeting sustained write performance requirements, particularly for Quad-Level Cell (QLC) SSDs, due to inefficient identification of valid Logical Page Numbers (LPNs) during Garbage Collection (GC) operations, leading to increased Write Amplification Factor (WAF) and bank-to-bank collisions, which impact performance and cause host command timeouts.
Innovation Solution
The method involves dividing a Super Block (SB) into sections based on the size of the SB and volatile memory, generating SB Logical-to-Physical (L2P) bitmaps for each section, and creating a valid LPN bitmap during GC operations by analyzing loaded L2P pages, storing these bitmaps in non-volatile memory, and performing GC in a phased manner to reduce redundant data loading and collisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire Super Block LPN bitmap is generated before GC operations, then complete validity information is available for all LPNs, but the generation process is time-consuming and causes host command timeouts
Solution Approach 1:
The Super Block is divided into multiple sections, and the LPN bitmap generation is segmented accordingly. Instead of generating the entire bitmap at once, the system generates bitmap information for each section separately and processes GC operations in a phased manner, allowing host commands to proceed without timeout while maintaining complete validity information through incremental updates.
2Speed
If DRAM is used to cache the entire L2P Table, then fast access to validity information is achieved, but the memory cost and device complexity increase significantly
Solution Approach 1:
The L2P Table and associated bitmap structures are segmented and distributed across different memory types. Rather than requiring a single large DRAM cache, the system uses a hierarchical approach combining smaller DRAM/SRAM caches for frequently accessed sections with NAND flash storage for the complete table, reducing overall memory complexity while maintaining fast access paths for active GC operations.
Solution Approach 2:
Different sections of the L2P Table and bitmap structures are cached in different memory locations based on their access patterns. The system dynamically determines which sections to cache in volatile memory versus storing in non-volatile memory, optimizing the balance between access speed and memory resource utilization without requiring uniform high-speed caching of the entire table.
3Productivity
If GC operations are performed without knowing valid LPNs in advance, then the GC process can proceed, but Write Amplification Factor increases and GC efficiency decreases
Solution Approach 1:
The system performs preliminary generation of section-level LPN bitmap information before initiating GC operations. By having even partial bitmap information available in advance for the current section being processed, the GC operation can identify valid LPNs beforehand, avoiding unnecessary writes and reducing Write Amplification Factor while maintaining high throughput through the phased processing approach.
Data Source
AI summary
A method for generating valid Logical Page Number (LPN) bitmap for a storage device may include dividing a Super Block (SB) into a plurality of sections, generating at least one SB Logical-to-Physical (L2P) bitmap (SBL2P bitmap) for at least one section of the plurality of sections of the SB, in response to a write request from a host device associated with the at least one section of the SB, each set bit of the SBL2P bitmap indicating that valid data is stored in at least one LPN in the at least one section of the SB, and generating a valid LPN bitmap corresponding to the SB in response to a Garbage Collection (GC) operation based on the generated at least one SBL2P bitmap, each bit of the valid LPN Bitmap representing validity information of data stored in a corresponding physical location of the SB.