Photocurrent-Reducing Display Device Structure
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Solution Overview
Problem
Conventional displaying devices, such as TFT LCDs, experience photocurrent leakage due to the photosensitivity of amorphous silicon layers, especially when exposed to light during manufacturing processes like the five-mask and four-mask processes, leading to unwanted photocurrent generation.
Innovation Solution
The solution involves modifying the manufacturing process by forming a gate electrode and a gate insulating layer on a substrate, followed by a g-aSi region positioned above the gate electrode, with source and drain metal regions separated by a passivation layer and connected via a conductive layer, specifically using a transparent conductive material to bridge and electrically connect the metal regions, thereby reducing photocurrent leakage by minimizing light reflection and direct exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the a-Si layer pattern is indented into the gate electrode to reduce photocurrent leakage, then photocurrent leakage is reduced, but light reflection between metal layers still causes photocurrent leakage
Solution Approach 1:
An intermediate reflective prevention layer is introduced between the first and second metal layers to block light reflection paths. This mediator layer prevents photons from reflecting between metal layers and reaching the a-Si layer, thereby eliminating the photocurrent leakage issue without requiring complex structural modifications to the existing indented a-Si layer design
Solution Approach 2:
The optical properties of the intermediate layer are specifically designed to have high reflectivity or light-blocking capability in the wavelength range relevant to backlight illumination. By changing the optical parameters (reflectivity, absorption coefficient) of this intermediate layer, the patent effectively blocks reflected light while maintaining electrical functionality
2Ease of manufacture
If the a-Si layer and second metal layer are formed in the same layer mask (four-mask process), then manufacturing process is simplified, but light directly projects onto the a-Si layer causing higher photocurrent leakage
Solution Approach 1:
The intermediate reflective prevention layer serves as a mediator that allows the four-mask simplified process to maintain low photocurrent leakage. By placing this light-blocking layer between the first metal layer and second metal layer, reflected light is prevented from reaching the a-Si layer, enabling the use of the simpler four-mask process without sacrificing photocurrent control
Solution Approach 2:
The harmful light reflection path is extracted and blocked by the intermediate layer, separating the light transmission function from the metal layer structure. This allows the a-Si layer and second metal layer to be formed in the same mask without direct light exposure to the a-Si layer through reflection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces photocurrent leakage by ensuring that light passes through without reflecting off metal layers, as the g-aSi region is indented within the gate electrode and the conductive connections are made using transparent materials, enhancing the display device's performance.
Implementation Method 1
The conductive layer is formed on the passivation layer and covers the first via and the second via for electrically connecting the DL metal region and the drain metal region
Implementation Method 2
The passivation layer is formed on the gate insulating layer and covers the source metal region, the drain metal region and the DL metal region
Implementation Method 3
forming a gate insulating layer for covering the gate electrode
Data Source
AI summary
A displaying device includes a substrate, a gate electrode formed on the substrate, a gate insulating layer, a gate a-Si region covering the gate electrode, a source metal region, a drain metal region, a data-line (DL) metal region, a passivation layer and a conductive layer. The gate a-Si region is formed on the gate insulating layer. The source and drain metal regions are formed on the gate a-Si region. The DL metal region is formed on the gate insulating layer and separated from the drain metal region at an interval. The passivation layer formed on the gate insulating layer covers the source, drain, and DL metal regions. The first and second vias of the passivation layer expose partial surfaces of the DL and drain metal regions respectively. The conductive layer formed on the passivation layer covers the first and second vias for electrically connecting the DL and drain metal regions.