3D Photonic-Electrical Package Bonding Without TSVs or Wire Bonds

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor technologies face challenges in efficiently integrating optical and electrical devices due to high interference and the need for costly through-silicon vias and wire-bond connections, which hinder efficient light coupling and high-frequency signal transmission.

Innovation Solution

A 3D package integration of photonic and electrical devices using index matching materials on the backside of optical devices for improved light coupling, eliminating the need for through-silicon vias and wire-bond connections, and incorporating metal reflectors to enhance light interference, allowing direct high-frequency signal transmission.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through-silicon via and wire-bond connections are used for integrating optical and electrical devices, then electrical connectivity is achieved, but parasitic interference increases and manufacturing cost increases

Engineering Contradiction:
Improvesignal transmission qualityVSAvoidparasitic interference
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent extracts and eliminates the harmful through-silicon via and wire-bond connection structures from the integration process. By removing these traditional interconnection methods, the patent eliminates the parasitic interference and inductance they introduce, while maintaining electrical connectivity through alternative direct bonding approaches between photonic and electronic devices

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary substrate or carrier that enables direct bonding between photonic and electronic devices without requiring through-silicon vias or wire bonds. This intermediary structure facilitates electrical connectivity while minimizing parasitic effects by providing a low-inductance path for signal transmission

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of manufacture

If through-silicon via connections are used, then electrical devices can be connected, but manufacturing cost increases and area is consumed

Engineering Contradiction:
Improvedevice integrationVSAvoidmanufacturing process complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent removes the complex through-silicon via formation process from the manufacturing sequence. By eliminating the need to drill, etch, and fill deep vias through the silicon substrate, the patent significantly simplifies the manufacturing process while maintaining device integration capability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent transitions from vertical through-silicon via connections to a different dimensional approach, using surface-level or near-surface bonding interfaces. This dimensional change allows electrical connectivity to be achieved without penetrating through the entire silicon thickness, thereby simplifying manufacturing

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If wire-bond connections are used for light coupling, then optical devices can be connected, but light coupling efficiency decreases and manufacturing cost increases

Engineering Contradiction:
Improveoptical device integrationVSAvoidlight coupling efficiency
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent extracts and eliminates wire-bond connections from the optical coupling path. By removing this indirect mechanical coupling method, the patent enables direct optical coupling between photonic devices, thereby restoring light coupling efficiency while maintaining manufacturing feasibility

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical wire-bond coupling system with a direct optical coupling mechanism. This substitution eliminates the mechanical constraints and inefficiencies of wire bonding, allowing light to couple directly between optical components with high efficiency

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances light coupling efficiency, reduces parasitic interference, and enables high-frequency signal transmission up to 250 Gbps per channel without the need for costly processes, freeing up area for additional electrical devices.

Implementation Method 1

index matching materials on the backside of optical devices for improved light coupling

Methodology Applied
Scientific EffectRefraction: Refraction

Implementation Method 2

incorporating metal reflectors to enhance light interference

Methodology Applied
Scientific EffectInterference: Interference

Implementation Method 3

incorporating metal reflectors to enhance light interference

Methodology Applied
Scientific EffectReflection: Reflection

Data Source

PatentUS20250357450A1Integrated packages having electrical devices and photonic devices and methods of manufacturing the same
Publication Date: 2025.11.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250357450A1 patent drawing
  • US20250357450A1 patent drawing
  • US20250357450A1 patent drawing

AI summary

A method for making semiconductor packages may comprise: forming a photonic die; forming an electrical die; and bonding the photonic die to the electrical die. Forming the photonic die may comprise: forming a grating coupler over a first silicon substrate; forming a plurality of first interconnect structures over the grating coupler; and forming an index matching material extending from a backside surface of the first silicon substrate to the oxide layer. Forming the electrical die may comprise: forming a plurality of transistors over a frontside surface of a second silicon substrate; and forming a plurality of second interconnect structures over the transistors. At least some of the first interconnect structures can be electrically connected to some of the second interconnect structures.