Photonic Interposer Tiles for Low-Power Chip Communication
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Solution Overview
Problem
Modern computing systems face scalability limitations due to power consumption, thermal issues, and bandwidth constraints, particularly in inter-chip and intra-chip communications, with existing electrical interconnects being power-hungry and bandwidth-limited.
Innovation Solution
The use of photonic interposers with programmable photonic tiles and optical connections, enabling low-power, high-bandwidth communication between chips and supporting heterogeneous architectures, allowing for flexible network topologies and efficient thermal management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If electrical interconnects are used for chip communication, then ease of manufacture is improved, but power consumption increases and bandwidth is limited
Solution Approach 1:
The patent replaces electrical interconnects with photonic interconnects using light instead of electricity for data transmission. This substitution fundamentally changes the communication medium from electrical signals through metal traces to optical signals through waveguides, thereby reducing power consumption while maintaining manufacturability through standard semiconductor fabrication processes
Solution Approach 2:
The patent changes the fundamental parameter of signal transmission from electrical to optical domain. By using photonic tiles with optical waveguides, modulators, and detectors, the system achieves higher bandwidth and lower power consumption while maintaining compatibility with existing manufacturing techniques through wafer-level integration
2Ease of manufacture
If electrical interconnects are used for chip communication, then ease of manufacture is improved, but bandwidth is limited
Solution Approach 1:
The patent replaces electrical interconnects with photonic interconnects using light instead of electricity for data transmission. This substitution fundamentally changes the communication medium from electrical signals through metal traces to optical signals through waveguides, thereby reducing power consumption while maintaining manufacturability through standard semiconductor fabrication processes
Solution Approach 2:
The patent introduces a three-dimensional stacked architecture with photonic tiles at different vertical levels, enabling communication in the vertical dimension. This 3D organization allows multiple layers of photonic tiles to communicate simultaneously, dramatically increasing overall system bandwidth while maintaining ease of manufacture through wafer-level stacking
3Use of energy by moving object
If photonic interposers are used for communication, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent merges multiple photonic tiles into a single integrated photonic interposer that can accommodate multiple different chips. By consolidating the photonic infrastructure at the interposer level rather than integrating it into each individual chip, the system reduces overall device complexity while maintaining low power consumption through shared optical resources
Solution Approach 2:
The patent creates a universal photonic interposer platform that can support multiple different chip types and configurations. The standardized photonic tile design with interchangeable photonic chips allows the same interposer infrastructure to serve multiple functions and applications, reducing complexity through reusability while maintaining energy efficiency
4Productivity
If photonic interposers with 3D stacking are used, then bandwidth is increased, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary alignment and bonding of photonic tiles at the wafer level before final packaging. By establishing precise optical connections between stacked photonic tiles during the manufacturing process rather than during system assembly, the system achieves high bandwidth through 3D stacking while managing manufacturing precision requirements through advance preparation and standardized interfaces
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The photonic interposers provide high-bandwidth, low-latency communication and thermal management, supporting scalable computing architectures with reduced power consumption and improved coherence across memory chips.
Implementation Method 1
each programmable interconnection comprises a waveguide crossing and an active coupler
Implementation Method 2
a first set of bus waveguides optically coupled to the transceiver, a second set of bus waveguides
Implementation Method 3
The transceiver comprises a plurality of modulators, coupled to a first bus waveguide of the first set of bus waveguides, tuned at different wavelengths relative to one another; and a plurality of drop filters, coupled to a second bus waveguide of the first set of bus waveguides, tuned at different wavelengths relative to one another
Implementation Method 4
The transceiver comprises a plurality of modulators, coupled to a first bus waveguide of the first set of bus waveguides, tuned at different wavelengths relative to one another
Implementation Method 5
each of the plurality of photonics tiles further comprises a 2×2 coupler coupling the transceiver to the first bus waveguide of the first set of bus waveguides
Implementation Method 6
each of the plurality of photonics tiles further comprises an interferometer having an input and first and second outputs, and a resonant filter
Implementation Method 7
each of the plurality of photonics tiles further comprises an interferometer having an input and first and second outputs, and a resonant filter
Data Source
AI summary
Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.