Physical Addressing for Side-Channel-Resistant Shared GPU Caching

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Solution Overview

Problem

Microarchitectural side channel attacks leak sensitive data through shared microarchitectural resources in multi-tenancy caching, which is becoming increasingly critical with the ubiquity of GPUs in datacenters.

Innovation Solution

Implementing side-channel resistant shared GPU caching by using physical addressing and secure I/O operations via Trusted Execution Environment (TEE)-I/O support, ensuring secure virtualization and isolation of compute partitions with unique encryption keys.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multi-tenancy caching is implemented in GPU systems, then resource sharing and productivity are improved, but side-channel attacks and data security deteriorate

Engineering Contradiction:

Improveresource sharing efficiencyVSAvoidside-channel attacks

Core Design Contradiction:

ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the cache memory into separate physical cache spaces for different virtual machines, with each VM having its own dedicated cache memory. This physical segmentation prevents side-channel attacks by isolating the microarchitectural resources (cache) for each tenant, eliminating the shared resource vulnerability while maintaining multi-tenancy productivity benefits through efficient resource allocation across multiple isolated cache spaces

Inventive Principle:

Principle #1Segmentation

2Reliability

If physical addressing is used for cache memory, then data integrity and security are improved, but address translation complexity increases

Engineering Contradiction:

Improvedata integrityVSAvoidaddress translation mechanism

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces an intermediary address translation mechanism that maps virtual addresses to physical cache addresses. This intermediary layer (address translation unit) handles the complexity of address translation centrally, allowing each VM to use virtual addressing for simplicity while the translation mechanism ensures physical addressing is used for actual cache access, thereby maintaining data integrity without exposing complexity to the virtual machines

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS20250291723A1Side-channel resistant shared GPU caching while using physical addressing

Publication Date: 2025.09.18 INTEL CORP

AI summary

One embodiment provides a graphics processor comprising a memory interface, a processing resource cluster including a plurality of processing resources, and a cache coupled with the memory interface and the processing resource cluster. The cache includes side-channel resistance circuitry to configure a side-channel resistance setting for the cache. In one embodiment, the side-channel resistance circuitry configures side-channel resistance by configuring cache isolation settings to facilitate side-channel resistance. The cache isolation setting adjusts a balance between side-channel resistance and performance for the cache by configuring how many cache ways and/or sets are isolated vs shared between contexts.