Physical Layer Register Access With Shadow Register Caching
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Solution Overview
Problem
Existing Ethernet PHY register access methods, such as synchronous MDIO/MDC interface, are slow and block the processor, leading to high load and reduced throughput in time-critical and high-density systems.
Innovation Solution
Implementing an enhanced MIIM controller with a scanning function that autonomously reads and caches data into shadow registers, reducing processor blocking time by performing scheduled and event-triggered MDIO operations independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If synchronous MDIO/MDC interface is used for PHY register access, then data can be read from PHY registers, but processor blocking time increases and throughput decreases
Solution Approach 1:
The patent extracts the PHY register access function from the main processor by implementing a dedicated eMIIM controller with scanning capability. The controller autonomously performs MDIO transactions to read PHY registers, separating this time-consuming operation from the main processor workflow. This extraction eliminates processor blocking while maintaining the ability to access PHY register data through shadow registers.
Solution Approach 2:
The patent introduces shadow registers as an intermediary data structure between the PHY registers and the main processor. The eMIIM controller reads PHY registers and stores copies in shadow registers, allowing the processor to access PHY data without directly blocking on MDIO transactions. This intermediary mechanism decouples the processor from the slow MDIO interface.
2Reliability
If processor directly accesses PHY registers via MDIO interface, then accurate PHY data can be obtained, but processor load increases
Solution Approach 1:
The eMIIM controller with scanning capability performs PHY register reads autonomously without requiring processor intervention. The controller self-manages the MDIO transactions, address decoding, and data transfer to shadow registers. This self-service approach maintains accurate PHY data access while eliminating the processor load that would otherwise be required to manage each individual register read operation.
3Loss of information
If multiple PHY registers are accessed sequentially, then all register data can be retrieved, but access time increases
Solution Approach 1:
The scanning function performs preliminary reads of multiple PHY registers and stores them in shadow registers before the processor needs the data. By pre-fetching and caching register data in shadow registers, the system eliminates the need for sequential access at the time of data retrieval. The controller proactively populates shadow registers with complete PHY state information, making all register data immediately available to the processor without sequential access delays.
Data Source
AI summary
An apparatus includes: a physical layer device (PHY); a PHY management interface; and a multiport Ethernet device coupled with the PHY via the PHY management interface. The multiport Ethernet device may include: a processor; a set of registers accessible to the processor via an internal bus of the multiport Ethernet device; a management interface controller to construct management frames at the PHY management interface; and a logic circuit to initiate copy of data from a register of the PHY via the management interface controller and store copied PHY register data at the register of the multiport Ethernet device.