Physical Partition Clock Design with Distance-Based Delay Balancing
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Solution Overview
Problem
Integrated circuit chip designers face challenges in achieving timing closure due to varying logical scales and clock tree sizes in separate physical partition structures, leading to unsatisfactory timing sequences and the need for repeated analysis between layers.
Innovation Solution
A clock design method that adjusts the delay of clock nodes based on distance from the system clock, connecting each circuit logic to corresponding nodes to converge timing, eliminating the need for repeated layer analysis.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate physical partition structures are used with different logical scales, then design flexibility and modularity are improved, but timing closure difficulty increases due to varying clock tree sizes
Solution Approach 1:
The patent applies local quality by creating different clock tree structures tailored to each physical partition's specific needs. Each partition receives customized clock distribution with adjusted delays based on its logical scale and timing requirements, rather than using a uniform clock distribution approach. This allows each partition to be optimized independently while maintaining overall system timing closure.
Solution Approach 2:
The patent changes clock tree parameters (such as clock period, phase, and delay values) for different physical partitions to achieve timing closure. By adjusting these parameters locally in each partition based on its specific logical scale and timing violations, the system maintains design flexibility while resolving timing issues without requiring repeated full-chip analysis.
2Device complexity
If uniform clock distribution is used across all physical partitions, then clock design simplicity is improved, but timing sequence accuracy deteriorates due to varying distances from system clock
Solution Approach 1:
The patent implements local quality by assigning different clock delay values to different physical partitions based on their distance from the system clock and their specific timing requirements. This localized clock distribution approach ensures that each partition receives appropriately timed clock signals, maintaining timing sequence accuracy while avoiding the complexity of a fully customized point-to-point clock distribution system.
Solution Approach 2:
The patent segments the clock distribution system into multiple physical partitions, each with its own clock tree structure and delay characteristics. This segmentation allows the clock system to be designed in manageable modules while achieving precise timing control in each partition, balancing design simplicity with timing accuracy.
3Manufacturing precision
If repeated layer analysis is performed between physical partitions, then timing closure accuracy is improved, but design time increases significantly
Solution Approach 1:
The patent applies preliminary action by pre-calculating and pre-configuring clock tree structures and delay values for each physical partition before final timing closure. By establishing appropriate clock distribution parameters in advance based on partition characteristics, the system achieves timing closure with minimal iterative analysis, significantly reducing design time while maintaining accuracy.
Solution Approach 2:
The patent introduces clock delay adjustment mechanisms as intermediaries between the system clock and individual partitions. These intermediaries (such as delay elements or buffer stages) allow timing adjustments to be made locally without requiring repeated full-system analysis, enabling accurate timing closure to be achieved efficiently.
Data Source
AI summary
A clock design method for two or more physical partition structures based on a same system clock. The method includes determining a distance of each circuit logic from the system clock; based on the distance between each circuit logic and the system clock, obtaining a plurality of clock nodes from the system clock to cause a delay of each clock node compared to the system clock to change with the distance from each circuit logic and the system clock, the greater the distance, the greater the delay; connecting each circuit logic to a corresponding clock node based on size of each circuit logic and the distance; and converging timing of each circuit logic by adjusting the delay of each clock node compared to the system clock.