Optical Pick-Up Head Sampling Interface for Voltage Isolation
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Solution Overview
Problem
Existing interface circuits between optical pick-up heads and CD-ROM control chips face issues with signal weakening and noise reduction when transmitting voltages across different working voltages, leading to potential chip damage and reduced signal noise rate.
Innovation Solution
The use of P-TYPE metal oxide semiconductor (PMOS) devices in conjunction with a boost circuit and sample and hold circuits to manage and regulate voltages, reducing the load on the optical pick-up head, enhancing signal noise rate, and improving sampling time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage divider resistors are used to weaken the writing voltage, then the input end oxide layer is protected from collapsing, but additional current is consumed and thermal noise is generated
Solution Approach 1:
The patent introduces a level shifting circuit as an intermediary component between the optical pick-up head and the CD-ROM control chip. This level shifting circuit acts as a mediator that translates the high voltage writing signal (3.3V-5V) to the appropriate low voltage level (1.4V-2.8V) for the control chip, eliminating the need for voltage divider resistors and their associated power consumption and thermal noise issues.
2Manufacturing precision
If larger resistance values are used in the voltage divider, then the writing voltage is better controlled under 3 volts, but the settling time of the SOP increases and sampling time is reduced
Solution Approach 1:
The level shifting circuit serves as an intermediary that provides precise voltage translation without the time-delay issues of resistive voltage dividers. The circuit design ensures fast settling time while maintaining accurate voltage control, allowing the SOP to complete sampling within the required time window.
3Adaptability or versatility
If the voltage divider weakens the reading voltage, then the signal can be processed by the control chip, but the signal noise rate (SNR) is reduced
Solution Approach 1:
The level shifting circuit acts as an intelligent intermediary that selectively processes different voltage signals. For reading voltages (1.4V-2.8V), it provides direct pass-through or minimal processing to preserve signal integrity and maximize SNR. For writing voltages (3.3V-5V), it performs the necessary voltage translation. This selective mediation maintains both voltage compatibility and signal quality.
4Manufacturing precision
If two resistors are used for voltage division, then the voltage can be controlled, but a large area of the chip is occupied
Solution Approach 1:
The patent merges the voltage control function into an integrated level shifting circuit that occupies significantly less chip area compared to discrete voltage divider resistors. The level shifting circuit combines multiple functions (voltage translation, signal buffering, and protection) into a single compact integrated block, reducing the overall chip area requirement while maintaining precise voltage control capability.
Data Source
AI summary
A system of sampling interface for an optical pick-up head comprises an optical pick-up head, a PMOS, a boost circuit, and a sample and hold circuit. The optical pick-up head outputs one of a reading voltage and a writing voltage. The PMOS gate receives the gate voltage and then the PMOS is turned on to pass the reading voltage to the sample and hold circuit. Moreover, the substrate of the PMOS receives a control voltage. The boost circuit is used to boost the gate voltage higher than the control voltage for turning off the PMOS and isolating the writing voltage.