Piezoelectric Layer Integration on Shielded Semiconductor Modules

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Solution Overview

Problem

Conventional bonding technologies in semiconductor manufacturing face challenges such as alignment accuracy, stability of bonding wires, high production costs, and poor controllability, leading to low integration and performance of semiconductor devices.

Innovation Solution

A semiconductor module configuration that includes a substrate with semiconductor elements, a shielding structure, and a piezoelectric layer formed directly on the shielding structure without additional bonding processes, utilizing deposition or bonding technology to integrate the piezoelectric layer, thereby improving controllability and integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional bonding technology (wire bonding, flip chip, TSV) is used to stack semiconductor elements, then interconnections between elements can be established, but alignment accuracy deteriorates and bonding wire stability becomes poor

Engineering Contradiction:
Improvebonding wire stabilityVSAvoidalignment accuracy
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent merges the bonding wire and the semiconductor element into a single integrated structure. The bonding wire is formed as an extension of the electrode pattern directly on the semiconductor element, eliminating the need for separate bonding processes. This integration ensures perfect alignment between the bonding wire and the electrode, resolving the alignment accuracy issue while maintaining bonding stability through controlled formation processes.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces an intermediary layer (such as a conductive adhesive layer or extended electrode pattern) that serves as a bridge between the semiconductor element and the bonding wire. This intermediary structure facilitates precise alignment and stable connection by providing a larger bonding area and better mechanical support, thereby improving both alignment accuracy and bonding wire stability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If additional bonding processes are used to stack semiconductor elements, then interconnections can be made, but production cost increases and controllability of individual elements deteriorates

Engineering Contradiction:
Improvecontrollability of semiconductor elementVSAvoidproduction cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent combines multiple bonding operations into a single integrated formation process. The bonding wire is formed simultaneously with the electrode pattern using the same deposition and patterning steps, eliminating the need for separate bonding processes. This reduction in process steps lowers production costs while improving controllability, as each semiconductor element can be processed and connected in a more controlled, sequential manner rather than through multiple complex bonding operations.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The semiconductor element structure is designed to be self-connecting through its own electrode extensions that automatically form the bonding wires. The electrode pattern on each element extends beyond the element boundary, serving as both the functional electrode and the bonding connection. This self-service approach eliminates the need for external bonding processes, reducing costs and improving individual element controllability.

Inventive Principle:
Principle #25Self-service

3Productivity

If conventional bonding technology is used, then semiconductor elements can be stacked, but integration consistency deteriorates due to poor controllability

Engineering Contradiction:
Improveintegration consistencyVSAvoidcontrollability of individual semiconductor element
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent merges the electrode formation and bonding wire creation into a single process step. The conductive material is deposited and patterned to form both the functional electrodes and the bonding wire extensions simultaneously. This unified approach ensures consistent integration across all semiconductor elements, as the same process parameters apply to all elements, improving both productivity and controllability.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the formation parameters of the bonding wire from separate bonding process parameters to deposition and patterning process parameters. By controlling the bonding wire formation through standard semiconductor fabrication parameters (deposition thickness, patterning dimensions, etch selectivity), the process becomes more controllable and consistent across different elements, improving integration consistency while maintaining reliability.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances the reliability and performance of semiconductor modules by eliminating alignment issues and unstable bonding wire quality, reducing production costs, and increasing integration consistency.

Implementation Method 1

a piezoelectric layer is formed on the shielding structure

Methodology Applied
Scientific EffectPiezoelectric effect: Piezoelectric Effect

Data Source

PatentUS12433165B2Method for manufacturing semiconductor module including piezoelectric layer
Publication Date: 2025.09.30 UNITED MICROELECTRONICS CORP
  • US12433165B2 patent drawing
  • US12433165B2 patent drawing
  • US12433165B2 patent drawing

AI summary

A method for manufacturing a semiconductor module is provided. The method includes: providing a substrate, wherein the substrate comprises a front side and at least one semiconductor element formed on the front side; forming a shielding structure on the at least one semiconductor element; forming a piezoelectric layer on the shielding structure.