Ultra-High-Density Capacitor Pillar Structures on Both Wafer Sides
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor capacitors have capacitance densities that are not high enough for many applications, and increasing density through traditional methods like narrower or deeper pillar structures makes them mechanically fragile and costly, while using high-k dielectric materials also increases expenses and process complexity.
Innovation Solution
A method of manufacturing high-density capacitors by forming 3D structures on both sides of a silicon substrate using multi-lobe pillars or trenches, with through-wafer vias filled with a conductor-dielectric-conductor layer stack, allowing simultaneous processing of both wafer sides and achieving ultrahigh-density capacitors with area capacitance exceeding 400 nF/mm² through a low-cost process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If narrower or deeper pillar structures are used to increase capacitance density, then capacitance density is improved, but mechanical strength deteriorates and manufacturing cost increases
Solution Approach 1:
The invention transitions from traditional planar capacitor layouts to three-dimensional pillar structures that extend vertically through the substrate. By utilizing the third dimension (depth) for capacitance accumulation, the design achieves higher capacitance density without requiring narrower features that would compromise mechanical strength. The pillars can be spaced wider apart while maintaining high density through their vertical extent.
Solution Approach 2:
The capacitor structure is segmented into multiple conductive layers separated by dielectric materials, forming a stacked configuration within each pillar. This segmentation allows capacitance to be accumulated across multiple interfaces (conductor-dielectric-conductor stacks), increasing total capacitance without reducing pillar dimensions or spacing, thereby maintaining mechanical robustness.
2Quantity of substance
If high-k dielectric materials are used to increase capacitance density, then capacitance density is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The invention achieves higher capacitance density by changing the geometric parameters of the capacitor structure (creating deep pillar structures with large surface area) rather than changing the material parameter (dielectric constant). This allows the use of standard silicon dioxide or other conventional dielectric materials that are already part of the CMOS fabrication process, avoiding the need for specialized high-k material deposition processes.
Solution Approach 2:
The invention uses standard semiconductor fabrication processes (etching, depositing, doping) that are already well-established in the industry to create the three-dimensional pillar structures. By copying and adapting existing process modules rather than introducing new high-k dielectric deposition techniques, the solution maintains compatibility with conventional manufacturing lines while achieving ultra-high density.
3Quantity of substance
If traditional single-sided capacitor structures are used, then manufacturing is simpler, but capacitance density is limited
Solution Approach 1:
The invention utilizes both top and bottom surfaces of the substrate to form pillar structures, effectively doubling the available area for capacitor formation. The through-substrate pillars connect conductive regions on opposite sides, creating capacitance pathways that extend through the entire substrate thickness. This bidirectional approach dramatically increases capacitance density without proportionally increasing process complexity.
Solution Approach 2:
The same fabrication processes (etching, depositing, doping) are used to create both the pillar structures and the through-substrate vias, making the process multi-functional. The pillars serve dual purposes: as mechanical support structures and as capacitor elements. This universality allows complex three-dimensional functionality to be achieved without adding separate dedicated process steps.
Data Source
Figure 1~2a
Figure 2b~2d
Figure 2e~2f
AI summary
The present invention describes an ultra High-Density Capacitor design, integrated in a semiconductor substrate, preferably a Si substrate, by using both wafer sides. The capacitors are pillar-shaped and comprise electrodes (930,950) separated by a dielectric layer (940).Via connections (920) are provided in trenches that go through the whole thickness of the wafer.