Semiconductive Pillar Contact Layout to Reduce DRAM Shorting
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Solution Overview
Problem
The challenge in semiconductor device design is to increase integration density and performance while preventing inadvertent shorting between components, particularly as feature dimensions and spacing decrease, which can lead to electrical shorts and device failure.
Innovation Solution
The design incorporates semiconductive pillar structures with angled end portions relative to the central portion, increasing the distance between storage node contact regions and bit line contact regions, and using advanced patterning techniques like pitch quadrupling and spacer-assisted double patterning to form these structures, reducing the likelihood of shorting and enhancing mechanical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature dimensions and spacing are reduced to increase integration density, then packing density increases, but the likelihood of inadvertent shorting between contacts increases
Solution Approach 1:
The pillar structure employs asymmetric geometry where the top portion has a smaller cross-sectional area than the base portion. This asymmetric design allows the pillar to maintain mechanical stability and structural integrity while occupying less lateral space at the contact level, thereby reducing the risk of shorting between adjacent contacts while preserving high integration density in the vertical dimension.
Solution Approach 2:
The invention transitions from a conventional planar contact layout to a three-dimensional pillar structure. By extending the contact structure vertically with a tapered geometry, the design utilizes the vertical dimension to increase packing density without proportionally reducing lateral spacing, thereby maintaining adequate separation between contacts and reducing shorting risk while achieving higher integration density.
2Quantity of substance
If contact spacing is reduced to increase packing density, then active area per unit volume increases, but mechanical stability decreases
Solution Approach 1:
The asymmetric pillar structure with a wider base and narrower top provides a stable mechanical foundation. The larger base area at the lower portion ensures adequate mechanical support and anchoring in the substrate, while the reduced top area allows for closer spacing of pillar structures, thereby achieving high packing density without compromising mechanical stability.
Solution Approach 2:
By introducing vertical dimensionality with the tapered pillar structure, the design achieves high packing density through vertical extension rather than lateral compression. This dimensional transition allows closely spaced pillars to maintain mechanical stability through their broad bases while achieving high active area per unit volume through the vertical profile.
Data Source
AI summary
A microelectronic device comprises semiconductive pillar structures each individually comprising a digit line contact region disposed laterally between two storage node contact regions. At least one semiconductive pillar structure of the semiconductive pillar structures comprises a first end portion comprising a first storage node contact region, a second end portion comprising a second storage node contact region, and a middle portion between the first end portion and the second end portion and comprising a digit line contact region, a longitudinal axis of the first end portion oriented at an angle with respect to a longitudinal axis of the middle portion. Related microelectronic devices, electronic systems, and methods are also described.