Semiconductor Storage Device Pillar Displacement Layout
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Solution Overview
Problem
Existing semiconductor storage devices face challenges in improving operation reliability and reducing the memory cell array region, particularly in preventing complex bit line control calculations during write and read operations and minimizing the dummy region required for the replacement step.
Innovation Solution
The semiconductor storage device employs a layout where memory pillars are arranged with a specific pitch and displacement in the X direction, and the slit regions are obliquely disposed relative to the memory trenches, allowing for simplified bit line control and reduced memory cell array size by aligning bit lines with the same attribute and reducing the dummy region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If memory pillars are arranged with conventional pitch and alignment, then the memory cell array region is larger, but the layout is simpler and easier to manufacture
Solution Approach 1:
The patent applies asymmetry by displacing even-numbered memory pillars from their conventional aligned positions. Specifically, even-numbered memory pillars are shifted by a first distance in a first direction, while odd-numbered pillars remain at standard positions. This asymmetric arrangement reduces the memory cell array region by optimizing space utilization, while the displacement distance is carefully controlled to maintain manufacturability within existing process capabilities.
Solution Approach 2:
The patent introduces dimensional optimization by considering pillar positions in multiple directions (first direction and second direction perpendicular to it). The displacement in the first direction combined with the perpendicular second direction creates a staggered two-dimensional arrangement that reduces the overall array footprint compared to conventional one-dimensional alignment, while maintaining regular spacing patterns that are manufacturable.
2Measurement precision
If bit lines are controlled with complex calculations, then precise memory cell access is achieved, but the operation reliability decreases due to calculation complexity
Solution Approach 1:
The patent segments the memory pillar arrangement into odd-numbered and even-numbered groups with different positional characteristics. This segmentation allows bit line control to be simplified by treating each segment according to its specific displacement pattern, rather than using complex calculations for all pillars uniformly. The regular displacement pattern of even-numbered pillars creates predictable access paths that improve operation reliability.
Solution Approach 2:
The patent changes the positional parameter of even-numbered memory pillars by displacing them by a specific first distance in the first direction. This parameter change creates a regular pattern that simplifies the control logic for bit lines, as the displacement distance becomes a known constant that can be incorporated into the control scheme, reducing calculation complexity while maintaining precise memory cell access.
3Ease of manufacture
If dummy region is increased for replacement step, then manufacturing process is simplified, but the memory cell array region increases
Solution Approach 1:
The patent applies local quality by providing different displacement treatments to different groups of memory pillars. Odd-numbered pillars at standard positions and even-numbered pillars at displaced positions create local variations in the layout that optimize the replacement step process in specific regions without requiring extensive dummy regions across the entire array, thus reducing the overall memory cell array region.
Solution Approach 2:
The patent performs preliminary action by pre-displacing even-numbered memory pillars to optimized positions before the replacement step. This preliminary positioning reduces the need for extensive dummy regions during the replacement process, as the pillars are already arranged in a configuration that minimizes the required replacement area, thereby reducing the overall memory cell array region while maintaining ease of manufacture.
Data Source
AI summary
A semiconductor storage device includes first conductive layers stacked in a first direction and extend in a second direction; second conductive layers stacked in the first direction and extend in the second direction; third conductive layers that are electrically connected to the first conductive layers and the second conductive layers and stacked in the first direction; a first insulating layer and a second insulating layer sandwich the first conductive layer; a third insulating layer and a fourth insulating layer sandwich the second conductive layer; first pillars arranged in the second direction in the first insulating layer with a first distance; and second pillars arranged in the second direction in the second insulating layer with the first distance. Each of the second pillars is displaced from a corresponding one of the first pillars by a second distance that is shorter than a half of the first distance in the second direction.