Pillar Structure Etching for Gate-All-Around Nanowire FETs
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating thin, vertical pillar structures for gate-all-around nanowire field effect transistors, particularly at technology nodes smaller than N5, due to difficulties in achieving uniform critical dimensions and scalability issues with existing lithographic and non-lithographic methods.
Innovation Solution
A method involving dry plasma etching with a patterned hard mask layer stack, using a first and second plasma to split the semiconductor layer, improving critical dimension uniformity and reducing footing in pillar structures, enabling the production of thin vertical pillar structures suitable for vertical gate-all-around nanowire field effect transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If lithographic methods including patterning and etching are used to produce thin vertical pillar structures, then the scalability for advanced technology nodes is improved, but the critical dimension uniformity and yield deteriorate
Solution Approach 1:
The patent divides the single etching process into multiple sequential etching steps with different conditions. The first etching step uses a first plasma process to remove material down to a first depth, and the second etching step uses a second plasma process to remove material down to a second depth, achieving different etch rates and selectivities for different portions of the pillar structure
Solution Approach 2:
The patent applies different plasma conditions locally to different regions of the pillar structure. The first plasma process parameters (power, pressure, gas composition) are optimized for the upper portion, while the second plasma process parameters are optimized for the lower portion, creating locally optimized etching conditions that improve overall critical dimension uniformity
2Manufacturing precision
If non-lithographic methods such as VLS mechanism and MBE are used to produce thin pillar structures, then the critical dimension control is improved, but the assembly difficulty and manufacturing complexity increase
Solution Approach 1:
The patent replaces complex non-lithographic growth methods (VLS, MBE) with conventional lithographic patterning combined with plasma etching. This substitution maintains critical dimension control through process optimization while avoiding the assembly difficulties and manufacturing complexity inherent in non-lithographic approaches
3Reliability
If thick pillar structures are used to compensate for lithographic limitations, then the manufacturing yield is improved, but the suitability for advanced technology nodes deteriorates
Solution Approach 1:
The patent changes multiple process parameters including plasma power, pressure, gas composition, and etch step sequencing to achieve the desired pillar dimensions and morphology. By optimizing these parameters, the process produces pillars with appropriate dimensions for advanced technology nodes while maintaining high manufacturing yield through controlled, repeatable processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances critical dimension uniformity and yield in pillar structure fabrication, allowing for the production of vertical gate-all-around nanowire field effect transistors with improved channel region uniformity, addressing scalability and performance challenges at advanced technology nodes.
Implementation Method 1
The semiconductor layer is dry plasma etched using the patterned hard mask layer stack as a mask. The dry plasma etching of the semiconductor layer includes subjecting the structure to a first plasma. Subjecting the structure to the first plasma removes a first part of the semiconductor layer
Data Source
AI summary
A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.