Gate Hard Mask Retention for Vertical Pillar Integrity and Resistance
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Solution Overview
Problem
The existing methods for fabricating semiconductor devices with vertical channels face issues such as pillar pattern bending, exposure during impurity region isolation, and increased word line resistance due to the loss of gate hard mask layers and inadequate etch selectivity.
Innovation Solution
A method involving the formation of pillar patterns with a thinner gate hard mask layer, using nitride layers, and employing mask patterns to etch and insulate the conductive layers without an etch-back process, ensuring the pillar patterns are protected and the word line resistance is reduced.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thick gate hard mask layer pattern is formed to compensate for loss during etch-back process, then the gate electrode can be formed properly, but the pillar pattern becomes bent due to excessive weight applied to the narrow pillar neck
Solution Approach 1:
The patent removes the etch-back process step entirely, extracting the problematic weight application mechanism. By forming the gate electrode through direct deposition on the pillar pattern without removing the gate hard mask layer, the excessive weight that causes pillar bending is eliminated while still achieving proper gate electrode formation.
Solution Approach 2:
The gate hard mask layer is formed with a thickness that accounts for the spacer formation process, but the layer is retained rather than removed. This preliminary consideration of the full process chain allows the gate hard mask layer to serve dual purposes: as an etch barrier during spacer formation and as a structural support that prevents pillar bending, while still enabling proper gate electrode formation.
2Area of stationary object
If the space between pillar patterns is reduced to increase memory density, then the unit memory cell area decreases, but the pillar pattern becomes exposed during trench etching due to inadequate etch selectivity
Solution Approach 1:
The patent employs a composite mask structure consisting of the gate hard mask layer (first oxide layer) and the spacer (second oxide layer). This composite structure provides enhanced etch selectivity and protection during the trench etching process, preventing pillar pattern exposure even when the space between pillars is reduced for higher density.
Solution Approach 2:
The gate hard mask layer and spacer are formed beforehand to create a protective cushion around the pillar pattern. This pre-formed protective structure compensates for the reduced spacing between pillars, ensuring that the pillar pattern remains protected during subsequent etching processes despite the tighter pitch.
3Area of stationary object
If the width of the gate electrode is reduced to increase memory density, then the unit memory cell area decreases, but the word line resistance increases due to the inverse proportionality between resistance and area
Solution Approach 1:
The patent merges the gate hard mask layer with the gate electrode structure by retaining the gate hard mask layer as part of the final gate electrode assembly. This merging allows the gate electrode to have an effective larger area (including the gate hard mask layer area) than would be possible with the conductive layer alone, thereby reducing word line resistance while maintaining high memory density.
Solution Approach 2:
The gate hard mask layer serves multiple functions: it acts as an etch barrier during spacer formation, provides structural support to prevent pillar bending, and contributes to the effective area of the gate electrode to reduce resistance. This multi-functionality allows the structure to achieve high density without sacrificing electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents pillar pattern bending and exposure, reduces word line resistance, and enhances the reliability and yield of semiconductor devices with vertical channels by maintaining the integrity of the gate hard mask layers and improving etch selectivity.
Implementation Method 1
the etch selectivity of the hard mask layer pattern 18 is not suited to an etchant gas used for etching the substrate 11
Implementation Method 2
filling a gap between the pillar patterns with a first conductive layer
Implementation Method 3
etching the first conductive layer using the first hard mask layer pattern as an etch barrier
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a plurality of pillar patterns on a substrate, filling a gap between the pillar patterns with a first conductive layer, forming a first hard mask layer pattern over the pillar patterns adjacent in one direction, etching the first conductive layer using the first hard mask layer pattern as an etch barrier, forming a second hard mask pattern over the pillar pattern adjacent in the other direction that crosses the one direction, and forming a gate electrode surrounding the pillar patterns by etching the first conductive layer etched using the second hard mask layer pattern as an etch barrier.