Pillar-Shaped Semiconductor Memory Device Defect Reduction
Solution Overview
Problem
Existing vertical NAND-type flash memory devices face challenges in forming tunnel insulating layers, interlayer insulation films, and word-line electrodes with high reliability and low defects, which are essential for achieving high-density and cost-effective memory devices.
Innovation Solution
A pillar-shaped semiconductor memory device is designed with a specific structure that includes a semiconductor pillar, tunnel insulating layer, data charge storage insulating layer, interlayer insulating layers, and conductor layers, where the side surfaces of the interlayer insulating layers are separated by a distance, and the conductor layers are formed in a way that they protrude towards the interlayer insulating layers during heat treatment, enhancing data retention and reducing defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods are used to form tunnel insulating layers and interlayer insulation films around semiconductor pillars, then the manufacturing process is simpler, but the reliability and defect reduction are insufficient
Solution Approach 1:
The patent applies preliminary action by forming a sacrificial organic substance layer on the semiconductor pillar surface before forming the tunnel insulating layer. This preliminary layer serves as a foundation that enables subsequent layers to be formed with better adhesion and fewer defects, directly improving reliability without significantly complicating the overall process
Solution Approach 2:
The organic substance layer acts as an intermediary between the semiconductor pillar and the tunnel insulating layer. This intermediate layer facilitates better interface quality and reduces defects at the critical semiconductor-insulator interface, thereby improving the reliability of the tunnel insulating layer formation
2Manufacturing precision
If conventional deposition methods are used for forming conductor layers and insulation films, then the manufacturing process is faster, but the manufacturing precision and defect reduction are inadequate
Solution Approach 1:
The patent segments the deposition process into distinct stages: first forming the organic substance layer, then the tunnel insulating layer, followed by the conductor layer, and finally the interlayer insulation film. This segmentation allows each layer to be optimized independently for precision while maintaining overall productivity through systematic process organization
Solution Approach 2:
The patent applies local quality by creating specific structural features at critical locations, such as the protruding portions of conductor layers that extend toward interlayer insulation films. This localized structural optimization improves manufacturing precision at critical interfaces without requiring全面提升 of the entire deposition process
3Reliability
If tunnel insulating layers and interlayer insulation films are formed with close spacing, then the device density is higher, but the data retention and defect reduction are compromised
Solution Approach 1:
The conductor layer serves as an intermediary structure between closely spaced tunnel insulating layers and interlayer insulation films. The protruding portions of the conductor layer create controlled spacing and electrical separation, enabling high device density while maintaining data retention reliability through proper electrical isolation
4Shape
If conventional heat treatment methods are used, then the processing time is shorter, but the protrusion formation of conductor layers toward interlayer insulating layers is insufficient
Solution Approach 1:
The patent applies parameter changes by optimizing heat treatment conditions (temperature, atmosphere, duration) to achieve the desired protrusion shape of conductor layers toward interlayer insulating layers. By carefully controlling these parameters, the conductor layers develop the necessary geometric features for improved electrical contact and field distribution without requiring excessive processing time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a high-reliability, high-density NAND-type flash memory device with reduced defects and improved data retention, achieved through precise formation of insulating and conductor layers, thereby addressing the challenges of existing technologies.
Implementation Method 1
the conductor layers are formed in a way that they protrude towards the interlayer insulating layers during heat treatment
Data Source
AI summary
A pillar-shaped semiconductor memory device includes a silicon pillar, and a tunnel insulating layer, a data charge storage insulating layer, a first interlayer insulating layer, and a first conductor layer, which surround an outer periphery of the silicon pillar in that order, and a second interlayer insulating layer that is in contact with an upper surface or a lower surface of the first conductor layer. A side surface of the second interlayer insulating layer facing a side surface of the first interlayer insulating layer is separated from the side surface of the first interlayer insulating layer with a distance therebetween, the distance being larger than a distance from the side surface of the first interlayer insulating layer to a side surface of the first conductor layer facing the side surface of the first interlayer insulating layer.