PIM Memory Bank Architecture for Data Transfer Bottlenecks
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Solution Overview
Problem
Existing semiconductor memory devices experience bottlenecks due to separate processor and memory functions, leading to inefficient data transmission and limited arithmetic operation speed, particularly in applications like neural networks and IoT systems.
Innovation Solution
Integration of computation circuits within the memory device, allowing parallel processing of internal and external data during different time periods, enhancing arithmetic operation speed by reusing internal data and supplying external data during shorter intervals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a completely separate processor and memory architecture is used, then memory function is simple and reliable, but data transmission between processor and memory creates bottlenecks and reduces processing speed
Solution Approach 1:
The patent merges the processor and memory into a single integrated device, where computation circuits are embedded within the memory structure. This allows arithmetic operations to be performed directly within the memory device without requiring data to be transmitted to a separate processor, thereby eliminating the data transmission bottleneck and significantly improving arithmetic operation speed.
Solution Approach 2:
The integrated memory device performs multiple functions simultaneously: it serves as both storage memory and computation processor. The computation circuits within the memory device can execute arithmetic operations on data stored in the memory banks, enabling the device to function as both a memory device and a processor, thus resolving the separation issue.
2Productivity
If data is transmitted between separate processor and memory, then memory structure remains simple, but large amounts of data must be transmitted leading to frequent bottlenecks
Solution Approach 1:
By combining the processor and memory into one integrated device, the patent eliminates the need for data transmission between separate components. Computation circuits within the memory device can directly process data stored in memory banks, significantly reducing data transmission time and improving overall data processing efficiency.
Solution Approach 2:
The computation circuits are pre-integrated within the memory device structure, ready to perform arithmetic operations immediately when data is loaded into the memory banks. This preliminary preparation of computation capabilities within the memory eliminates the need for subsequent data transmission to an external processor.
3Speed
If computation circuits are integrated within memory device, then arithmetic operation speed increases, but device structure becomes more complex
Solution Approach 1:
The patent segments the memory device into distinct functional modules: memory banks for data storage and computation circuits for arithmetic operations. This segmentation allows each component to be optimized independently while working together as an integrated system, managing the complexity through modular organization.
Solution Approach 2:
The patent introduces a new dimensional organization by embedding computation circuits within the memory structure itself, creating a three-dimensional integration where computation and storage coexist spatially. This dimensional change allows multiple functions to occupy the same physical space without requiring separate external components.
4Productivity
If internal data is read completely before external data is supplied, then data processing is simple, but processing time increases due to waiting for internal data read
Solution Approach 1:
The patent performs preliminary actions by reading internal data from memory banks before external data is fully supplied to the computation circuits. This allows the computation circuits to start processing as soon as internal data is ready, without waiting for external data transmission to complete, thereby reducing overall processing time.
Solution Approach 2:
The computation circuits continuously perform arithmetic operations by alternating between processing internal data and receiving external data. This continuous operation pattern ensures that the computation circuits are always busy performing useful work rather than idle waiting, maximizing processing speed and minimizing time loss.
Data Source
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AI summary
A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.