PIM Memory Command Prioritization for Internal Processing
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Solution Overview
Problem
Existing memory devices face performance degradation due to slow data retrieval and writing operations, limited memory bandwidth, and complexity in performing arbiter and virtual memory management functions during internal processing, leading to inefficiencies in computational workloads and cache coherence issues.
Innovation Solution
A memory device with a processor-in-memory (PIM) architecture that offloads arbiter and virtual memory management functions to a host, allowing internal processing operations to be performed by a PIM within the memory device, simplifying hardware configurations and enabling efficient data transactions and processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the memory device performs arbiter function and virtual memory management function internally, then internal processing can be performed, but hardware configuration becomes complex and difficult
Solution Approach 1:
The patent extracts the arbiter function and virtual memory management function from the memory device and relocates them to the host. The memory device simply receives commands from the host and executes internal processing operations, while the host's CPU handles arbitration and memory management tasks. This separation reduces the memory device's hardware complexity while maintaining internal processing capability.
2Productivity
If the memory device performs internal processing operations, then computational workload is reduced, but data retrieval and writing operations become a bottleneck
Solution Approach 1:
The patent introduces a command queue as an intermediary mechanism between the host and the memory device's internal processor. The command queue stores prepared commands and allows the internal processor to fetch instructions without frequent host intervention. This mediator enables the internal processor to operate more independently, reducing the bottleneck effect of data retrieval and writing operations.
Data Source
AI summary
Provided is a method of performing an internal processing operation of a memory device in a system including a host device and the memory device. The memory device includes a memory cell array and a processor-in-memory (PIM) performing an internal processing operation. In an internal processing mode, by the PIM, the memory device performs the internal processing operation based on internal processing information stored in the memory cell array. When the internal processing information is an internal processing operation command indicating a type of the internal processing operation, the memory device outputs the internal processing operation command including an internal processing read command and an internal processing write command to the host device. The host device issues to the memory device a priority command determined from among a data transaction command and the internal processing operation command.