PIM Memory Device PEIO Gating Circuit Data Collision Prevention
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Solution Overview
Problem
Current memory devices face challenges in preventing data collisions during operation processing, which can lead to performance deterioration and inefficiencies, especially in high-performance electronic systems like neural networks.
Innovation Solution
A memory device with a processor-in-memory (PIM) circuit and a processing element input and output (PEIO) gating circuit that controls the electric connection between bank local IO and bank group IO lines, allowing data to be processed without being transmitted to the memory bank, thereby optimizing data paths and preventing collisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transmitted through both bank local IO and bank group IO during operation processing, then data availability is improved, but data collisions occur leading to performance deterioration
Solution Approach 1:
The patent segments the data transmission paths into separate channels: bank local IO lines for local bank operations and bank group IO lines for group-level operations. The PEIO gating circuit selectively activates one path at a time based on the operation type, preventing data collisions while maintaining processing efficiency. This segmentation allows independent control of data flow through different paths.
Solution Approach 2:
The patent implements dynamic path selection through the PEIO gating circuit, which changes the electric connection state between bank local IO and bank group IO based on the operation mode. During memory operations, the circuit connects bank local IO to banks; during operation processing, it connects bank group IO to PIM circuit. This dynamic switching prevents collisions while optimizing performance for each operation type.
2Speed
If electric connection between bank local IO and bank group IO is maintained for memory operations, then memory access speed is improved, but data collisions occur during operation processing
Solution Approach 1:
The PEIO gating circuit dynamically switches the electric connection configuration based on operation type. For memory operations (read/write), it maintains connection between bank local IO and banks for high speed. For operation processing, it switches to connect bank group IO to PIM circuit, isolating the paths to prevent collisions. This dynamic reconfiguration resolves the contradiction between speed and reliability.
Solution Approach 2:
The PEIO gating circuit acts as an intermediary device that controls and mediates the electric connection between bank local IO and bank group IO. It selectively connects or isolates these paths based on the current operation mode, preventing direct interference between memory operations and operation processing, thus ensuring both speed and reliability.
3Reliability
If data paths are isolated through PEIO gating circuit for operation processing, then data collision prevention is improved, but additional control complexity is introduced
Solution Approach 1:
The PEIO gating circuit is designed as a universal control mechanism that handles multiple operation types (memory read, memory write, operation processing) through a single unified structure. It responds to operation codes to automatically configure the appropriate data path, eliminating the need for separate control circuits for each operation type. This multi-functionality reduces overall control complexity while maintaining reliable path isolation.
Data Source
AI summary
A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO.