Pin Card Optical Semiconductor Switch Parasitic Capacitance
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Solution Overview
Problem
High-cost MEMS switches are required for high-frequency semiconductor test apparatuses, which increases the cost significantly due to their high cost and low DC breakdown voltage, making them unsuitable for mass-production test apparatuses with hundreds to thousands of channels.
Innovation Solution
A pin card design utilizing a low-cost optical semiconductor switch with impedance circuits to reduce parasitic capacitance effects, allowing high-frequency performance without the need for expensive MEMS switches, by using impedance circuits with ferrite beads, resistors, and inductors to control the control signal and reduce parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If MEMS switches are used to achieve high-frequency performance, then the high-frequency signal transmission capability is improved, but the cost increases significantly
Solution Approach 1:
The patent replaces expensive MEMS switches with inexpensive composite semiconductor switches. Although semiconductor switches have limitations at very high frequencies, the patent uses them in a cost-effective manner for mass-production test apparatuses with multiple channels, achieving acceptable performance at significantly lower cost.
Solution Approach 2:
The patent changes the operating parameters of the semiconductor switch by carefully controlling the test pattern frequency to be within the switch's capabilities (below several GHz). It also adjusts the DC breakdown voltage parameter by designing the switch configuration to handle DC components through proper biasing and circuit design.
2Ease of manufacture
If composite semiconductor switches are used to reduce cost, then the cost is reduced, but the DC breakdown voltage becomes too low to handle DC components
Solution Approach 1:
The patent introduces an intermediary element - a DC block capacitor - in series with the semiconductor switch. This capacitor blocks DC components from reaching the switch while allowing AC test signals to pass through, thereby protecting the switch from DC breakdown while maintaining signal transmission capability.
Solution Approach 2:
The patent segments the signal path into AC and DC components, using the semiconductor switch for AC signal switching and a separate DC blocking mechanism to handle DC components. This segmentation allows each component to be optimized for its specific function.
3Ease of manufacture
If semiconductor switches are used instead of MEMS switches, then the cost is reduced, but the high-frequency performance deteriorates due to parasitic capacitance
Solution Approach 1:
The patent converts the harmful effect of parasitic capacitance into a beneficial design consideration by carefully selecting operating frequencies that work within the switch's capacitance limitations. It uses the parasitic capacitance as a known parameter to optimize the overall system design rather than trying to eliminate it completely.
Solution Approach 2:
The patent employs dynamic switching strategies where the switch state is carefully controlled based on the input signal characteristics. By dynamically adjusting the switching timing and duration, the system maximizes the effective bandwidth while minimizing the impact of parasitic capacitance on high-frequency performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves improved high-frequency performance and reduces the overall cost of the test apparatus by using low-cost optical semiconductor switches, maintaining high-frequency capabilities while minimizing the impact of parasitic capacitance, thus supporting mass-production test operations effectively.
Implementation Method 1
an optical semiconductor switch which has a first terminal connected to an AC test unit and a second terminal connected to an input/output terminal and a DC test unit, and is capable of switching states, according to control signals input to positive and negative control terminals thereof
Implementation Method 2
impedance circuits with ferrite beads, resistors, and inductors to control the control signal and reduce parasitic capacitance
Data Source
AI summary
A DUT is connected to an I/O terminal. An AC test unit performs an AC test operation for the DUT. A DC test unit performs a DC test operation for the DUT. An optical semiconductor switch is arranged such that a first terminal thereof is connected to the AC test unit and a second terminal thereof is connected to the I/O terminal. The optical semiconductor switch 10 is configured to be capable of switching states, according to control signals input to control terminals, between a connection state in which the first terminal and the second terminal are connected to each other, and a disconnection state in which they are disconnected from each other. A first impedance circuit is arranged on a signal line for the control signal to be input to the positive-electrode control terminal. Furthermore, a second impedance circuit is arranged on a signal line for the control signal to be input to the negative-electrode control terminal.