Pin Layout Method for Multi-Patterning Accessibility
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Solution Overview
Problem
In the semiconductor industry, the use of multi-patterning technology for fabricating small critical pitch semiconductor chips reduces pin accessibility due to stricter patterning rules, making it challenging to maintain high pin accessibility similar to single patterning technology.
Innovation Solution
A method and system for pin layout that categorizes pins into cross-track, fat, and short types, using electronic design automation tools to assign pin accesses to specific patterning groups and adjust spacings to ensure reliable connections and enhanced accessibility, while adhering to multi-patterning rules, by extending pin accesses or adding wires as needed during the placement and routing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multi-patterning technology is used to reduce critical pitch and enhance feature density, then manufacturing precision is improved, but pin accessibility deteriorates due to stricter patterning rules
Solution Approach 1:
The pin layout is segmented into different types (cross-track pins, fat pins, short pins) with distinct placement rules. Each pin type is assigned to specific patterning groups and tracks, allowing the design tool to systematically manage pin accessibility constraints while adhering to multi-patterning requirements. This segmentation enables selective optimization of pin placements without compromising overall feature density.
Solution Approach 2:
The design tool performs preliminary assignment of pins to patterning groups and tracks during the placement stage, before routing begins. By pre-determining which pins can be accessed from which tracks based on multi-patterning rules, the tool eliminates accessibility conflicts that would otherwise arise during later routing operations, ensuring both high feature density and maintained pin accessibility.
2Productivity
If multi-patterning technology is used to enhance feature density, then productivity is improved, but device complexity increases due to additional patterning groups and tracks
Solution Approach 1:
The design tool dynamically adjusts layout parameters such as pin spacing, pin access extension length, and wire routing constraints based on the assigned patterning group and track. By automatically modifying these parameters according to multi-patterning rules, the tool manages the increased device complexity inherent in multi-patterning while maintaining high feature density, relieving designers from manually tracking numerous patterning constraints.
Data Source
AI summary
A computer readable storage medium encoded with program instructions, wherein, when the program instructions is executed by at least one processor, the at least one processor performs a method. The method includes selecting a cell, determining whether a pin has an area smaller than a predetermined area, allowing a pin access of the pin to extend in a corresponding patterning track of the pin access when the pin access when the pin is determined to be having an area smaller than the predetermined threshold, and causing an integrated circuit to be fabricated according to the pin.