Package-in-Package Semiconductor Device Using Through-Silicon Vias
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Solution Overview
Problem
Package-in-package (PIP) semiconductor devices face challenges with lengthy electrical signal paths and high complexity in design due to numerous conductive wires, leading to deteriorated electrical performance and increased fabrication costs, especially in vertically stacked configurations.
Innovation Solution
The implementation of through-silicon vias and through-mold vias in semiconductor dies and packages, respectively, to facilitate direct electrical connections between components, reducing the reliance on conductive wires and simplifying the electrical signal paths, while using encapsulant materials to form a package body that covers the components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive wires are used to interconnect electronic components in vertically stacked PIP devices, then electrical connections can be established, but the electrical signal paths become lengthened resulting in deteriorated electrical performance
Solution Approach 1:
The patent transitions from planar wire-based connections to vertical through-silicon via connections, changing the dimensional approach to electrical interconnection. The through-silicon vias extend vertically through the substrate, enabling direct electrical pathways that significantly reduce signal path length compared to traditional wire bonding methods in stacked configurations.
Solution Approach 2:
The patent extracts and eliminates the need for extensive conductive wire networks by implementing direct through-silicon via connections. This removes the intermediate wire layer and its associated signal path length, directly connecting electronic components through the substrate rather than using wires to route signals around or between components.
2Reliability
If a large number of conductive wires are used to facilitate electrical connections in PIP devices, then all electronic components can be interconnected, but the probability of shorting between conductive wires increases during encapsulation
Solution Approach 1:
The patent removes the conductive wire layer entirely from the encapsulation process by using through-silicon via connections that are integrated into the substrate structure. This eliminates the wire shorting hazard that occurs when encapsulant material bridges adjacent wires during the encapsulation process.
Solution Approach 2:
The patent merges the electrical connection function directly into the substrate structure through through-silicon vias, combining the substrate, connection pathways, and component mounting functions into a single integrated structure. This eliminates the need for separate wire interconnects that would be vulnerable to shorting during encapsulation.
3Adaptability or versatility
If increased numbers of electronic components are included in PIP devices, then device functionality is enhanced, but the design of electrically conductive patterns on the substrate becomes highly complex increasing fabrication difficulty and cost
Solution Approach 1:
The patent uses vertical through-silicon via connections to establish electrical pathways in the vertical dimension rather than relying on complex planar conductive patterns. This dimensional shift simplifies the substrate conductive pattern design, as connections are made through vertical vias rather than requiring intricate wire routing patterns across the substrate surface.
Solution Approach 2:
The patent segments the electrical connection function into discrete through-silicon via locations, allowing electronic components to be interconnected through predefined via positions rather than requiring continuous complex conductive patterns. This segmentation approach simplifies substrate design by reducing the conductive pattern complexity to essential via placements and trace routing.
Data Source
AI summary
In accordance with the present invention, there is provided multiple embodiments of a package-in-package semiconductor device including shortened electrical signal paths to optimize electrical performance. In each embodiment, the semiconductor device comprises a substrate having a conductive pattern formed thereon. In certain embodiments, a semiconductor package and one or more semiconductor dies are vertically stacked upon the substrate, and placed into electrical communication with the conductive pattern thereof. One or more of the semiconductor dies may include through-silicon vias formed therein for facilitating the electrical connection thereof to the conductive pattern of the substrate or to other electronic components within the vertical stack. Similarly, the semiconductor package may be provided with through-mold vias to facilitate the electrical connection thereof to other electronic components within the vertical stack. In other embodiments of the present invention, a semiconductor die which is electrically connected to the conductive pattern of the substrate is encapsulated with an inner package body which itself is formed to include through-mold vias used to facilitate the electrical connection thereof to another semiconductor die stacked thereon. In each embodiment of the semiconductor device, the vertically stacked electronic components thereof may be covered with a package body which also partially covers the substrate.