Pipe Gate Electrode Etch Stop for 3D Memory Block Division
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In nonvolatile memory devices with a 3-dimensional structure, the etching process for forming slits to divide word lines into memory blocks can damage structures under gate electrodes, such as pipe coupling transistors, leading to manufacturing challenges and increased costs.
Innovation Solution
A method involving the formation of pipe gate electrodes, first slits that divide the pipe gate electrode layer, and second slits that divide conductive layers by the unit of memory block, using dielectric layers and material layers with etch stop functionality to prevent damage to underlying structures during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If slits are formed to divide stacked word lines into memory blocks, then memory block division is achieved, but structures under gate electrodes (pipe coupling transistors) are damaged
Solution Approach 1:
The patent introduces an etch stop layer positioned between the gate electrode layer and the structures below (pipe coupling transistors). This intermediary layer prevents the etching process from damaging the underlying structures while still allowing the slits to be formed for memory block division. The etch stop layer acts as a protective mediator that enables the necessary manufacturing process without causing harm to critical components.
Solution Approach 2:
The etch stop layer is formed in advance before the slit formation process. This preliminary action ensures that the protective layer is already in place to prevent damage during the subsequent etching operation. By preparing the protective structure beforehand, the patent avoids the need for complex protective measures during the actual slit formation process.
2Productivity
If blanket processing is used to form memory cells on vertically stacked word lines, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the monolithic manufacturing process into distinct stages with different etching conditions. The first etching process forms initial slits with relaxed conditions, while the second etching process forms additional slits with controlled depth to stop at the etch stop layer. This segmentation of the manufacturing process reduces overall complexity by breaking down the blanket processing into manageable, independently optimized steps.
Solution Approach 2:
The patent employs different etching parameters for different processing stages. The first etching process uses parameters that allow deep penetration, while the second etching process uses parameters controlled to stop at the etch stop layer. By changing etching parameters (such as etch depth, etch rate, or stopping criteria) between processing steps, the patent manages manufacturing complexity while maintaining high integration density through blanket processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient division of memory blocks without damaging the pipe gate electrodes, reducing manufacturing costs and improving the integration density of nonvolatile memory devices.
Implementation Method 1
forming a first etch stop layer over the pipe gate electrode layer and over portions of the plurality of conductive layers; etching the first and second material layers by using the pipe gate electrodes as an etch stop layer
Data Source
AI summary
A nonvolatile memory device includes a pipe gate electrode layer formed over a substrate; a plurality of conductive layers stacked over the pipe gate electrode layer; source lines formed over an uppermost one of the conductive layers; first slits passing through the pipe gate electrode layer at positions overlapping with the source lines, and dividing the pipe gate electrode layer into a plurality of pipe gate electrodes, and second slits passing through the conductive layers at positions different from the first slits, and dividing the conductive layers into a plurality of memory blocks.