Pipeline Multi-Level Receiver With Fewer Sense Amplifiers
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently processing multi-level signals with reduced power consumption and circuit size while maintaining performance, particularly in receivers with pipeline structures for volatile and nonvolatile memory applications.
Innovation Solution
A receiver configuration that includes a sample and hold circuit, a first analog-to-digital converting circuit, a digital-to-analog converting circuit, and a second analog-to-digital converting circuit, which generates multi-bit data by sampling and holding input signals and selecting reference voltages based on output data bits, operating in a pipeline scheme to reduce the number of sense amplifiers and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional receiver structure is used to process multi-level signals, then the circuit can handle the signal, but the circuit size and power consumption increase
Solution Approach 1:
The receiver is divided into multiple pipeline stages, with each stage containing a sense amplifier and associated circuitry. This segmentation allows the total circuit to be distributed across stages, reducing the complexity burden on any single stage while maintaining overall signal processing capability through sequential processing.
Solution Approach 2:
The pipeline structure operates in periodic cycles where each stage processes signals in sequence through clocked operation. Data moves through the pipeline in discrete time steps, allowing circuit elements to be reused across different clock cycles and reducing the need for simultaneous operation of all circuit components.
2Reliability
If a conventional receiver structure is used to process multi-level signals, then the circuit can handle the signal, but the power consumption increases
Solution Approach 1:
By dividing the receiver into pipeline stages, power consumption is distributed across multiple clock cycles rather than being concentrated in a single stage. Each stage consumes power only during its active processing window, allowing for more efficient power management and reduced peak power requirements.
Solution Approach 2:
The clocked pipeline operation enables power gating techniques where circuit stages are activated only during their designated time windows. This periodic activation reduces average power consumption compared to continuously operating conventional structures, as inactive stages can be powered down or placed in low-power states.
3Device complexity
If the number of sense amplifiers is reduced to decrease circuit size, then the circuit becomes more compact, but the ability to process multi-level signals is degraded
Solution Approach 1:
The pipeline structure adds a time dimension to the processing architecture. Instead of requiring all sense amplifiers to operate simultaneously in space, the pipeline distributes processing across time, allowing fewer amplifiers to handle multi-level signals through sequential processing of different signal components across multiple clock cycles.
Data Source
AI summary
A receiver receiving a multi-level signal includes a sample and hold circuit, first and second analog-to-digital converting circuits, and a digital-to-analog converting circuit. The sample and hold circuit generates a sample data signal by sampling and holding an input data signal. The first analog-to-digital converting circuit generates a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages. The digital-to-analog converting circuit selects at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data. The second analog-to-digital converting circuit generates at least one additional bit of the output data based on the sample data signal and the at least one additional selection reference voltage.