Pipeline-Stage Circuit Equivalence Checking for Scalable LEC
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Solution Overview
Problem
Existing logical equivalence check (LEC) techniques for integrated circuits are unscalable for large circuits, taking decades to complete and are inefficient due to the NP-complete nature of using Satisfiability (SAT) and Satisfiability Modulo Theories (SMT) solvers, making them impractical for timely and robust checks.
Innovation Solution
The method involves performing LECs by determining pipeline stages in a circuit design, analyzing data transfer between these stages, and conducting LECs for each stage independently, using automation tools and solvers like Z3 SMT to compare high and low level representations, thereby reducing computation time and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional LEC techniques using SAT/SMT solvers are applied to large circuits, then completeness of equivalence check is improved, but computation time increases to decades making it unscalable
Solution Approach 1:
The circuit design is divided into multiple pipeline stages, and LEC is performed independently for each stage rather than on the entire circuit at once. This segmentation reduces the computational complexity from NP-complete for the whole circuit to manageable subproblems for each stage, enabling completion within reasonable timeframes while maintaining equivalence verification.
Solution Approach 2:
The methodology performs preliminary actions by first determining the pipeline stages of the circuit design before conducting LEC. By pre-structuring the circuit into stages and preparing the high-level and low-level representations for each stage in advance, the subsequent equivalence checking becomes more efficient and scalable.
2Reliability
If LEC is performed on entire circuit design at once, then equivalence verification is thorough, but efficiency decreases making it impractical for timely checks
Solution Approach 1:
The circuit design is divided into multiple pipeline stages, and LEC is performed independently for each stage rather than on the entire circuit at once. This segmentation reduces the computational complexity from NP-complete for the whole circuit to manageable subproblems for each stage, enabling completion within reasonable timeframes while maintaining equivalence verification.
3Loss of time
If pipeline stage decomposition is used for LEC, then computation time is reduced improving scalability, but device complexity increases due to stage determination and data transfer analysis
Solution Approach 1:
The circuit design is divided into multiple pipeline stages, and LEC is performed independently for each stage rather than on the entire circuit at once. This segmentation reduces the computational complexity from NP-complete for the whole circuit to manageable subproblems for each stage, enabling completion within reasonable timeframes while maintaining equivalence verification.
Solution Approach 2:
The methodology introduces pipeline stages as intermediary structures between the high-level and low-level circuit representations. These stages serve as intermediate representations that facilitate the equivalence checking process by breaking down the complex comparison into manageable segments while maintaining the overall equivalence relationship.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on computer storage media for performing logic equivalence check on a circuit design are described. In one aspect, a method includes receiving a request for performing operations of a logical equivalence check of a circuit design and determining, based on one or more criteria, to perform the operations using pipeline stages. In response to the determination, a plurality of pipeline stages of the circuit design that is in a high level representation are determined. For each stage of the plurality of pipeline stages, data corresponding to a high level representation of the stage are obtained, and data corresponding to a low level representation of the stage that corresponds to the high level representation of the stage are obtained. The high level representation and the low level representation are compared. An output is generated based on the comparison.