Pipeline-Stage Circuit Equivalence Checking for Scalable Verification
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Solution Overview
Problem
Existing logical equivalence check (LEC) techniques for integrated circuits are unscalable and inefficient, particularly for large circuits, taking decades to complete due to the NP-complete nature of using Satisfiability (SAT) and Satisfiability Modulo Theories (SMT) solvers, rendering them impractical for timely and robust checks.
Innovation Solution
The method involves performing LECs by determining pipeline stages in a circuit design, analyzing data transfer between stages, and comparing high-level to low-level representations for each stage independently, using SMT solvers like Z3 to ensure logical equivalence, thereby reducing computation time and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single LEC is performed on the whole circuit using SAT/SMT solvers, then logical equivalence can be verified, but the computation time becomes excessively long (decades for large circuits)
Solution Approach 1:
The circuit is divided into multiple pipeline stages, and LEC is performed separately for each stage rather than on the entire circuit at once. This segmentation reduces the computational complexity from NP-complete on the whole circuit to manageable sub-problems on individual stages, enabling verification to complete in reasonable time while maintaining reliability.
2Reliability
If LEC is performed on large circuit designs, then design correctness can be ensured, but existing techniques become unscalable and impractical
Solution Approach 1:
By segmenting large circuits into pipeline stages, the invention makes LEC scalable to large circuit designs. Each stage is verified independently, allowing the method to handle circuits of any size without becoming unscalable, thus ensuring design correctness even for complex large-scale integrated circuits.
Solution Approach 2:
The invention introduces a temporal dimension to the LEC process by verifying circuits stage-by-stage through the pipeline architecture. This transforms a single monolithic verification problem into a sequence of smaller verification steps, enabling scalability to large circuits that would otherwise be intractable.
3Reliability
If traditional LEC methods are used, then equivalence can be checked, but the cost and time requirements make them impractical for timely checks
Solution Approach 1:
Segmenting the verification process into pipeline stages dramatically improves productivity by enabling parallel or sequential verification of multiple stages. This approach maintains accurate equivalence checking while reducing overall verification time from decades to practical timeframes, making the process suitable for industrial production workflows.
Data Source
AI summary
Methods, systems, and apparatus, including computer programs encoded on computer storage media for performing logic equivalence check on a circuit design are described. In one aspect, a method includes receiving a request for performing operations of a logical equivalence check of a circuit design and determining, based on one or more criteria, to perform the operations using pipeline stages. In response to the determination, a plurality of pipeline stages of the circuit design that is in a high level representation are determined. For each stage of the plurality of pipeline stages, data corresponding to a high level representation of the stage are obtained, and data corresponding to a low level representation of the stage that corresponds to the high level representation of the stage are obtained. The high level representation and the low level representation are compared. An output is generated based on the comparison.