Verifying Functional Equivalence of Pipelined Designs with Memories
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Solution Overview
Problem
Verifying the functional equivalence of pipelined designs containing memories is computationally expensive due to the complexity of modern designs and the need for sequential equivalence checks, which are prohibitively costly and inefficient.
Innovation Solution
A system that abstracts memory operations into a combinational form, allowing for logical abstraction of memory systems and comparison of combinational outputs to verify functional equivalence, using memory mappings and symbolic simulation to determine correspondence and prove equivalence by induction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential equivalence check is used to verify memory contents, then verification completeness is improved, but computational cost increases prohibitively
Solution Approach 1:
The patent extracts memory operations from the sequential verification process and represents them in combinational form. By taking out the memory systems and replacing them with their operational effects in the combinational logic, the verification avoids the computationally expensive sequential equivalence check while maintaining verification completeness for the relevant design outputs.
Solution Approach 2:
The patent creates a correspondence between memory operations in the first design and the second design, effectively copying the memory behavior into the combinational representation. This allows the verification to check equivalence of the copied operational effects rather than simulating the full sequential memory behavior, reducing computational cost.
2Measurement precision
If detailed memory architecture verification is performed, then verification accuracy is improved, but verification time increases significantly
Solution Approach 1:
The patent extracts the essential operational correspondence of memory systems without requiring detailed verification of memory architecture. By representing memory operations combinationally, it verifies accuracy of memory effects on design outputs while avoiding time-consuming detailed architectural comparison.
Solution Approach 2:
The patent segments the verification process into two parts: (1) determining correspondence between memory operations at a high level, and (2) verifying combinational outputs. This segmentation allows verification accuracy to be maintained for critical paths while reducing overall verification time by avoiding detailed memory architecture analysis.
3Reliability
If pipelined designs with different pipeline depths are verified using traditional methods, then equivalence checking thoroughness is improved, but computational complexity increases prohibitively
Solution Approach 1:
The patent changes the representation parameter of memory operations from sequential to combinational form. This parameter change allows thorough equivalence checking of pipelined designs with different pipeline depths while avoiding the prohibitive computational complexity of traditional sequential verification methods.
Solution Approach 2:
The patent introduces combinational representation as an intermediary between the two pipelined designs. This intermediary allows equivalence checking to be performed on the combinational outputs without directly comparing the complex sequential behaviors of designs with different pipeline depths, reducing computational complexity while maintaining thoroughness.
Data Source
AI summary
One embodiment of the present invention provides a system that formally proves the functional equivalence of pipelined designs. First, the system receives a specification for a first pipelined design, which includes a first memory system, and a specification for a second pipelined design, which includes a second memory system. Next, the system determines a correspondence between operations on the first memory system and corresponding operations on the second memory system. This correspondence enables memory operations to be represented in a combinational form based on design inputs, thereby allowing both memory systems to be logically abstracted out of their respective designs. After the memory systems have been abstracted out, the system compares the combinational outputs of the first pipelined design and the combinational outputs of the second pipelined design to verify that the designs are functionally equivalent.