Pipelined State Metric Calculator for Parallel Trellis Decoding

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Solution Overview

Problem

The heavy processing burden associated with encoding and decoding data, particularly in the wireless communications sector, where convolutional encoding and decoding techniques like Viterbi and MAP algorithms require efficient calculation of state metrics to mitigate data transfer errors.

Innovation Solution

A state metric calculator is designed to calculate state metrics for sequence estimation techniques such as MAP or logMAP algorithms, utilizing a processing path with data stores to operate on different state metrics in parallel, enabling simultaneous calculation and correction of state metrics across multiple stages of a trellis, potentially implemented in ASICs or FPGAs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a state metric calculator processes multiple state metrics in parallel using pipelined architecture with data stores partitioning the processing path into sections, then the processing burden is reduced and efficiency is improved, but the device complexity increases

Engineering Contradiction:
Improveprocessing efficiencyVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The processing path is partitioned into multiple sections using data stores, with each section handling different operations (e.g., branch metric calculation, state metric calculation, correction) for different state metrics. This segmentation enables parallel processing of multiple state metrics simultaneously, improving throughput while managing complexity through modular design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporal dimension to the processing architecture by implementing pipelining, where different stages of the calculation process operate at different clock cycles. This allows the system to process multiple state metrics in parallel across different time steps, effectively increasing productivity without proportionally increasing the complexity of individual processing elements

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Speed

If the processing path is partitioned into sections operating on different state metrics in the same clock cycle, then the calculation speed is improved, but the manufacturing precision and operational complexity increase

Engineering Contradiction:
Improvecalculation speedVSAvoidoperational complexity
Core Design Contradiction:
SpeedVSEase of operation

Solution Approach 1:

The processing path is divided into distinct sections, each responsible for specific operations on different state metrics. This segmentation allows simultaneous execution of multiple operations in the same clock cycle, increasing calculation speed while maintaining operational clarity through functional separation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The data stores serve multiple functions: they partition the processing path, buffer data between stages, and enable parallel access to state metrics from different clock cycles. This multi-functionality reduces the need for separate dedicated components, simplifying the overall system while maintaining high calculation speed

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8914716B2Resource sharing in decoder architectures
Publication Date: 2014.12.16 ALTERA CORP
  • US8914716B2 patent drawing
  • US8914716B2 patent drawing
  • US8914716B2 patent drawing

AI summary

A state metric calculator for calculating state metrics of stages in a trellis of a sequence estimation technique is described. The calculator has a processing path containing operations needed for calculating a state metric of a trellis stage from state metrics of an earlier trellis stage. One or more data stores are located in the processing path to divide the path into separate sections. The sections can then operate on the production of different state metrics to one another in, if desired, the same clock cycle.