Pixel Structure Manufacturing with Auxiliary Patterns
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Solution Overview
Problem
In large-size display panels, the increased length of data lines and scan lines leads to higher resistance values and parasitic capacitance, causing RC delay effects, resulting in display issues like flickering, nonuniform brightness, and degraded quality.
Innovation Solution
A manufacturing method for a pixel structure that reduces the resistance values of scan lines and data lines by forming auxiliary patterns in parallel with them, using a halftone mask or slit mask for photoresist layer exposure, and employing a dual damascene process to connect these patterns electrically, thereby reducing line resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the size of display panel is increased, then the display area is enlarged, but the resistance values of data lines and scan lines increase due to their increased length
Solution Approach 1:
The patent introduces auxiliary patterns (first auxiliary pattern connected to data line, second auxiliary pattern connected to scan line) that are distributed along the length of the data and scan lines. These auxiliary patterns segment the long conductive paths into multiple shorter segments, reducing the overall resistance by providing parallel current paths and distributing the resistance load across multiple connection points.
Solution Approach 2:
The patent adds auxiliary patterns in the planar dimension (x-y plane) rather than extending the conductive paths in the third dimension. By placing multiple auxiliary patterns at different positions along the data and scan lines, the invention creates additional parallel pathways in the same physical space, effectively reducing resistance without increasing the panel's vertical profile.
2Manufacturing precision
If the resolution of display panel is increased, then the picture quality is improved, but the parasitic capacitance of lines increases
Solution Approach 1:
The auxiliary patterns segment the long continuous conductive lines into multiple shorter sections. By distributing capacitance loading across multiple smaller segments rather than one long continuous line, the effective parasitic capacitance impacting signal integrity is reduced, allowing higher resolution displays to maintain signal quality.
3Length of stationary object
If the length of data line and scan line is increased, then the display size is enlarged, but the RC delay effect becomes more obvious
Solution Approach 1:
By introducing auxiliary patterns that create parallel current paths, the patent segments the RC delay problem into multiple smaller time constants. The auxiliary patterns provide alternative current pathways that reduce the effective resistance and capacitance of any single path, thereby reducing the overall RC delay and enabling faster charging times across large display panels.
Solution Approach 2:
The patent changes the electrical parameters (resistance and capacitance) of the conductive paths by adding auxiliary patterns. This modifies the RC time constant parameter, reducing it from a large value (caused by long lines) to a smaller effective value that enables faster charging despite the increased physical line length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively addresses the display issues by minimizing resistance and capacitance, improving display quality by reducing flickering and nonuniform brightness, and enabling single-side drive for large-size panels.
Implementation Method 1
a single exposure and development is performed on the photoresist layer to form a first portion and a second portion
Data Source
AI summary
A method of manufacturing the pixel structure is provided. The method includes forming a gate, a scan line connected to the gate, and at least one auxiliary pattern on a substrate. An insulating layer, a semiconductor layer, an ohmic contact layer, and a photoresist layer are formed in sequence. Afterwards, a single exposure and development is performed on the photoresist layer to form a first portion and a second portion. Next, the ohmic contact layer and the semiconductor layer which are not covered by the photoresist layer are removed to expose a part of the insulating layer. Next, the second portion of the photoresist layer is removed. Subsequently, a part of the thickness of the semiconductor layer not covered by the first portion is removed and the exposed insulating layer is removed, so as to form a channel layer and an insulating layer.