Pixel Memory Cell Backplane Timing With Dummy Driver Matching
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Solution Overview
Problem
Existing backplanes for spatial light modulators face challenges in simultaneously driving wordlines and bitlines at high speeds and tight timing tolerances due to variations in components outside the pixel driver array, necessitating increased timing windows to account for mismatches.
Innovation Solution
Implementing an array of dummy pixel drivers outside the pixel driver array, aligned along the bitline and wordline directions, to mirror the configuration of actual pixel drivers and eliminate mismatches caused by semiconductor processing and temperature variations, ensuring consistent RC characteristics across the backplane.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dummy pixel drivers are implemented to mirror actual pixel drivers, then timing consistency and RC characteristic matching are improved, but device complexity increases
Solution Approach 1:
The patent implements dummy pixel drivers that are identical copies of actual pixel drivers, positioned at strategic locations (corners and edges) of the display array. These dummy drivers replicate the exact RC characteristics of real pixel drivers, providing reference signals for timing compensation without requiring complex additional circuitry. The copying approach ensures that dummy drivers experience the same processing variations and environmental conditions as actual drivers.
Solution Approach 2:
The dummy pixel drivers create equipotential reference points across the display array by mirroring the electrical characteristics of actual drivers. This establishes consistent voltage levels and timing references at multiple locations, compensating for variations in semiconductor processing and temperature gradients. The equipotential approach allows the system to maintain uniform timing windows across the entire display without increasing operational complexity.
2Reliability
If timing windows are increased to account for component variations, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent uses dummy pixel drivers to generate feedback signals that reflect actual timing conditions across the display array. These feedback signals are used to dynamically adjust timing windows and compensation values, allowing the system to maintain reliability with minimized timing margins. The feedback mechanism enables real-time compensation for processing variations without requiring fixed, conservative timing windows that would reduce data rate.
Solution Approach 2:
The system dynamically changes timing parameters based on measurements from dummy pixel drivers. By monitoring actual timing variations and adjusting compensation values accordingly, the system optimizes timing windows to be as small as possible while maintaining reliability. This parameter adjustment approach eliminates the need for fixed, oversized timing windows that would limit productivity.
3Manufacturing precision
If dummy pixel drivers are added to compensate for processing variations, then manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The patent implements dummy pixel drivers that are identical copies of actual pixel drivers, positioned at strategic locations (corners and edges) of the display array. These dummy drivers replicate the exact RC characteristics of real pixel drivers, providing reference signals for timing compensation without requiring complex additional circuitry. The copying approach ensures that dummy drivers experience the same processing variations and environmental conditions as actual drivers.
Solution Approach 2:
The dummy pixel drivers create equipotential reference points across the display array by mirroring the electrical characteristics of actual drivers. This establishes consistent voltage levels and timing references at multiple locations, compensating for variations in semiconductor processing and temperature gradients. The equipotential approach allows the system to maintain uniform timing windows across the entire display without increasing operational complexity.
Data Source
AI summary
A backplane design for delivering image data in an efficient manner to a memory cell forming a part of a pixel driver comprises a word line design and a column data register release signal delivery design that are speed matched and a complementary bit line delivery design that is speed matched to a row decoder signal circuit operative to pull a word line driver to a state to enable the memory circuits of that row to receive data from the column drivers for each column. The speed matching is effective over a range of operating temperatures because the circuit designs are substantially identical.