3D Pixel Capacitor Layout for High-Resolution Image Sensors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing image sensors face challenges in effectively forming elements on pixels due to the increasing number of pixels and decreasing pixel size, which affects capacitance and overall performance.
Innovation Solution
The image sensor is designed with optimized arrangements of capacitors and vias, including conductive plate layers, capacitor dielectric layers, and via structures that are diagonally disposed to enhance capacitance and connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels is increased and pixel size is decreased, then the resolution is improved, but the capacitance is reduced
Solution Approach 1:
The patent transitions from a planar capacitor structure to a three-dimensional stacked structure with multiple conductive plate layers arranged vertically. This dimensional change allows the capacitor to achieve sufficient capacitance in a reduced lateral area, enabling smaller pixel sizes while maintaining required capacitance values for proper pixel circuit operation.
Solution Approach 2:
The patent implements a nested structure where multiple conductive plate layers are stacked within a compact vertical space, with insulating layers positioned between them. This nesting approach maximizes the capacitance-generating surface area within the limited pixel footprint, allowing high capacitance in a small area to support higher resolution sensors.
2Measurement precision
If the number of pixels is increased and pixel size is decreased, then the resolution is improved, but the element formation becomes more difficult
Solution Approach 1:
The capacitor structure is segmented into multiple discrete conductive plate layers separated by insulating layers. This segmentation allows each layer to be formed using standard thin-film deposition and patterning processes, making the complex three-dimensional structure compatible with existing semiconductor manufacturing techniques despite the reduced pixel size.
Solution Approach 2:
The stacked capacitor structure serves multiple functions: it provides the required capacitance for pixel circuit operation, maintains a compact footprint for high-resolution arrays, and uses standard fabrication processes. This multi-functionality resolves the manufacturing difficulty by achieving high resolution without requiring specialized or overly complex formation processes.
3Quantity of substance
If via structures are added to connect capacitor plate layers, then the capacitance is improved, but the device complexity is increased
Solution Approach 1:
The patent combines multiple capacitor plate layers into a single integrated stacked structure with unified insulating and conductive layers. This merging approach creates a compact three-dimensional capacitor that achieves high capacitance without requiring separate discrete components or complex interconnection schemes, thus improving capacitance while limiting complexity growth.
Solution Approach 2:
By stacking conductive plate layers vertically in the third dimension rather than arranging them laterally in the plane, the patent reduces the number of via structures needed for interconnection. The vertical stacking allows capacitive elements to be connected through straightforward vertical vias rather than requiring complex lateral routing, improving capacitance density while controlling structural complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves capacitance and connectivity, enhancing the performance and dynamic range of the image sensor by optimizing the arrangement of capacitors and vias.
Implementation Method 1
Each of the pixels may include a photodiode and a pixel circuit for converting an electrical charge generated by the photodiode into an electrical signal
Implementation Method 2
an image sensor is provided that may assure capacitance by optimizing the arrangement of a capacitor and a via in a pixel including the capacitor
Data Source
AI summary
An image sensor includes: a substrate including a plurality of photoelectric conversion regions; capacitor structures on the substrate; a capacitor insulating layer in a spacing between the capacitor structures; and external via structures in the spacing between the capacitor structures and penetrating the capacitor insulating layer. The capacitor structures include: conductive plate layers stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the substrate; capacitor dielectric layers alternately stacked with the conductive plate layers; a first via structure penetrating the conductive plate layers, spaced apart from odd-numbered conductive plate layers, and in lateral contact with even-numbered the conductive plate layers; and a second via structure spaced apart from the first via structure, penetrating the conductive plate layers, spaced apart from the even-numbered conductive plate layers, and in lateral contact with the odd-numbered the conductive plate layers.