Pixel Capacitor Trench Layout for Low-Noise Image Sensors

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Solution Overview

Problem

Laminate-type image capture devices face challenges in reducing noise and miniaturization due to limitations in the layout of electrical connections and parasitic capacitance, which affect the quality and size of the imaging device.

Innovation Solution

The imaging device incorporates a first capacitive element with trench portions and multiple electrical contact points, allowing for increased freedom in wire layout, reduced parasitic capacitance, and enhanced capacitance value, while minimizing pixel area and noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional laminate-type structure with photoelectric conversion layer on insulating layer is used, then the device can achieve basic imaging function, but parasitic capacitance increases and wire layout freedom is limited

Engineering Contradiction:
Improvenoise reductionVSAvoidparasitic capacitance
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces trench portions that extend vertically into the substrate, utilizing the third dimension (depth) to create capacitive coupling paths. This allows electrical connections to be established through vertical trenches rather than only horizontal wire routing, thereby reducing parasitic capacitance in the planar direction while maintaining electrical connectivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The capacitive element is divided into multiple segments including first and second electrodes separated by dielectric layers, with trench portions creating distinct vertical zones. This segmentation allows independent optimization of each segment's electrical characteristics, enabling reduced parasitic capacitance while maintaining necessary capacitance values for noise reduction.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If more electrical contact points are added to increase wire layout freedom, then layout flexibility improves, but device area increases

Engineering Contradiction:
Improvewire layout freedomVSAvoidpixel area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent utilizes vertical trenches extending into the substrate to create multiple electrical contact points at different depths. This three-dimensional approach allows multiple connections to be established within a compact planar footprint, increasing wire layout freedom without proportionally increasing pixel area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The trench portions are nested within the pixel structure, with electrodes and dielectric layers arranged in concentric or nested configurations. This nesting allows multiple electrical contact points to be packed into a small area by utilizing vertical space and overlapping horizontal projections, thereby increasing layout flexibility without significant area penalty.

Inventive Principle:
Principle #7Nested doll (Nesting)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration reduces noise and allows for miniaturization of the imaging device by minimizing parasitic capacitance and increasing the degree of freedom in wire layout, leading to improved image quality and smaller pixel sizes.

Implementation Method 1

a first capacitive element including a first electrode provided above the semiconductor substrate, a second electrode provided above the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS20250098357A1Imaging device
Publication Date: 2025.03.20 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO LTD
  • US20250098357A1 patent drawing
  • US20250098357A1 patent drawing
  • US20250098357A1 patent drawing

AI summary

An imaging device includes a semiconductor substrate and pixels. Each of the pixels includes a first capacitive element including a first electrode provided above the semiconductor substrate, a second electrode provided above the semiconductor substrate, and a dielectric layer located between the first electrode and the second electrode. At least one selected from the group consisting of the first electrode and the second electrode has a first electrical contact point electrically connected to a first electrical element and a second electrical contact point electrically connected to a second electrical element different from the first electrical element. The first capacitive element includes at least one trench portion having a trench shape.