Pixel Circuit Layout for Higher Aperture Imaging Sensors

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Solution Overview

Problem

The existing semiconductor devices face limitations in reducing pixel area, aperture ratio, and power consumption due to shared elements and interconnected power sources, which restricts high-resolution and high-speed imaging capabilities.

Innovation Solution

A semiconductor device design that includes a pixel portion with separate switches and wiring for each pixel, allowing for independent power management and reduced area occupation, utilizing photoelectric conversion elements with selenium and oxide semiconductors to enhance imaging performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If elements such as transistors are shared by multiple pixels, then the pixel area is reduced, but the aperture ratio decreases due to occupied area in pixel region

Engineering Contradiction:
Improvepixel areaVSAvoidaperture ratio
Core Design Contradiction:
Area of stationary objectVSArea of moving object

Solution Approach 1:

The patent moves shared elements (transistors, switches, power source lines) from the two-dimensional pixel plane to a third dimension by placing them in a circuit region beneath or adjacent to the pixel array. This spatial reconfiguration allows pixel elements to be shared across multiple pixels without occupying additional area within the pixel region itself, thereby reducing pixel area while maintaining aperture ratio.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the semiconductor device into distinct functional regions: a pixel region containing photoelectric conversion elements and an independent circuit region containing shared transistors, switches, and power source lines. This segmentation allows the circuit region to serve multiple pixels simultaneously without interfering with the optical path or aperture of individual pixels.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If separate power source lines are provided for amplifier and reset transistor, then power management freedom increases, but pixel area increases due to space for two power source lines

Engineering Contradiction:
Improvepower management freedomVSAvoidpixel area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent implements separate power source lines (first power source line and second power source line) that extend across the circuit region to serve multiple pixels simultaneously. Each pixel can independently access these power source lines through switches, enabling separate power management for amplifiers and reset transistors without requiring additional space within the pixel region, as the power distribution infrastructure is shared across the entire array.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables a compact semiconductor device with improved power management, increased aperture ratio, and enhanced imaging capabilities, supporting high-resolution and high-speed imaging while reducing power consumption.

Implementation Method 1

utilizing photoelectric conversion elements with selenium and oxide semiconductors to enhance imaging performance

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Data Source

PatentUS20240015381A1Semiconductor device, imaging device, and electronic device
Publication Date: 2024.01.11 SEMICON ENERGY LAB CO LTD
  • US20240015381A1 patent drawing
  • US20240015381A1 patent drawing
  • US20240015381A1 patent drawing

AI summary

Provided is a novel semiconductor device, a semiconductor device with reduced area, or a versatile semiconductor device. The semiconductor device includes a pixel portion including a first pixel, a second pixel, a third pixel, and a fourth pixel; a first switch and a second switch located outside the first to fourth pixels; a first wiring located outside the first to fourth pixels; a second wiring electrically connected to the first and second pixels; and a third wiring electrically connected to the third and fourth pixels. A first terminal of the first switch is electrically connected to the first wiring. A second terminal of the first switch is electrically connected to the second wiring. A first terminal of the second switch is electrically connected to the first wiring. A second terminal of the second switch is electrically connected to the third wiring.