Pixel Circuit Layout for FD Addition Across Conversion Efficiency States
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Prior art imaging apparatuses can only perform addition readout based on the floating diffusion (FD) addition method in a low conversion efficiency state, limiting its applicability.
Innovation Solution
The imaging apparatus includes first and second pixel units with floating diffusions that convert charges into voltage, featuring switch transistors and capacitive elements to enable pixel addition and adjust conversion efficiency across multiple states, allowing addition readout even in higher efficiency states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the switch is in the non-conduction state to avoid adding parasitic capacitance to the FD node, then conversion efficiency is maintained, but addition readout based on FD addition cannot be performed
Solution Approach 1:
The pixel circuit is divided into separate components: the first switch transistor for selecting pixels, the second switch transistor for adding pixel signals, and the capacitive element for adjusting conversion efficiency. This segmentation allows each component to perform its specific function independently, enabling addition readout without compromising conversion efficiency.
Solution Approach 2:
A capacitive element is introduced as an intermediary between the floating diffusion node and the second switch transistor. This capacitive element acts as a buffer that adjusts the total capacitance at the FD node, thereby controlling conversion efficiency while allowing the addition readout function to operate through the second switch transistor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables addition readout based on FD addition in various conversion efficiency states, improving noise characteristics and charge quantity management for optimal ISO sensitivity settings.
Implementation Method 1
a floating diffusion that converts charges, transferred from a light-receiving unit, into voltage
Implementation Method 2
a capacitive element that is connected between another source/drain electrode of the third switch transistor and a reference potential node
Data Source
AI summary
A first and second pixel units that perform FD addition are provided. The first pixel unit includes: a first switch transistor of which one source/drain electrode is connected to an FD; and a reset transistor that is connected between another source/drain electrode of the first switch transistor and a power supply node. The second pixel unit includes: a second switch transistor of which one source/drain electrode is connected to an FD; a third switch transistor of which one source/drain electrode is connected to another source/drain electrode of the second switch transistor; and a capacitive element that is connected between another source/drain electrode of the third switch transistor and a reference potential node. The respective other source/drain electrodes of the first switch transistor and the second switch transistor are electrically connected with each other.