Pixel Circuit Signal Line Layout for Accurate PWM Dimming
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Solution Overview
Problem
The luminous efficiency of light-emitting devices in display apparatuses decreases under low current density conditions, and existing pulse width modulation (PWM) dimming methods suffer from low accuracy and signal interference in pixel circuits.
Innovation Solution
The array substrate includes independently controlled first and second light-emitting control signal lines for the first and second light-emitting control transistors, located in different conductive layers to reduce overlap and interference, and employs a phased PWM signal control to enhance dimming accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If PWM dimming method is used to adjust brightness, then luminous efficiency is improved, but signal interference between control signal lines occurs
Solution Approach 1:
The patent applies dimensional change by transitioning from planar signal line arrangement to three-dimensional stacked architecture. First and second light-emitting control signal lines are positioned in different conductive layers (first and second conductive layers respectively), with vertical separation achieved through multiple insulating layers. This spatial dimensionality resolves signal interference while maintaining PWM dimming functionality for improved luminous efficiency.
Solution Approach 2:
The patent segments the control signal transmission by dividing it into two independent paths: first light-emitting control signal line connected to first light-emitting control transistor and second light-emitting control signal line connected to second light-emitting control transistor. These segmented signal lines are electrically insulated from each other, preventing interference while enabling independent PWM control for enhanced luminous efficiency.
2Object-affected harmful factors
If multiple conductive layers are used to reduce signal interference, then manufacturing complexity increases
Solution Approach 1:
The patent implements multi-functionality where conductive layers serve dual purposes: first conductive layer contains both first light-emitting control signal line and first gate conductive layer patterns, while second conductive layer contains second light-emitting control signal line and second gate conductive layer patterns. This universal design reduces overall structural complexity despite using multiple layers, as each layer performs multiple functions simultaneously.
Solution Approach 2:
The patent merges signal line routing with gate electrode formation by integrating first light-emitting control signal line with first gate conductive layer and second light-emitting control signal line with second gate conductive layer. This merging approach simplifies manufacturing processes while achieving electrical insulation between control signal lines through the multi-layer structure.
3Object-affected harmful factors
If signal line orthographic projections do not overlap, then manufacturing precision requirements increase
Solution Approach 1:
The patent resolves positioning precision requirements by utilizing the vertical dimension through multiple conductive layers. First light-emitting control signal line and second light-emitting control signal line are positioned in different layers (first and second conductive layers respectively), separated by insulating layers. This vertical separation ensures no orthographic projection overlap while reducing sensitivity to planar positioning precision, as the primary separation mechanism operates in the third dimension.
Data Source
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AI summary
An array substrate. The array substrate comprises a substrate and a plurality of pixel circuits provided on the substrate, the plurality of pixel circuits being arranged in a plurality of rows and columns. Each pixel circuit comprises a first light-emitting control transistor and a second light-emitting control transistor. The array substrate further comprises a first light-emitting control signal line and a second light-emitting control signal line. The first light-emitting control signal line is electrically connected to gates of the first light-emitting control transistors. The second light-emitting control signal line is electrically connected to gates of the second light-emitting control transistors. The array substrate further comprises a plurality of conductive layers. The first light-emitting control signal line and the second light-emitting control signal line are electrically insulated from each other, the first light-emitting control signal line and the second light-emitting control signal line being located on different conductive layers, and the orthographic projections of the first light-emitting control signal line and the second light-emitting control signal line on the substrate not overlapping each other.