Pixel-on-DTI Image Sensor Layout for Short-Channel Noise Control
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Solution Overview
Problem
CMOS image sensors face challenges with smaller pixel dimensions and closer pixel spacing due to device scaling, leading to increased short channel effects and noise levels, which degrade performance and increase power consumption.
Innovation Solution
A CMOS image sensor with a pixel device overlying a deep trench isolation (DTI) structure, where the pixel device is directly arranged on the DTI structure, enhancing room for the pixel device and utilizing the DTI as an insulator to improve short channel effects and noise levels, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pixel dimensions are reduced and pixel spacing is decreased to increase pixel density, then productivity and integration density are improved, but short channel effects and noise levels increase, degrading device performance and increasing power consumption
Solution Approach 1:
The substrate is divided into multiple isolation regions by deep trench isolation structures, creating separate pixel units. This segmentation allows each pixel to be electrically isolated while maintaining high density, mitigating short channel effects through physical separation and enabling better control of noise and power consumption at scaled dimensions
Solution Approach 2:
Different regions of the substrate are given different electrical characteristics through selective doping and isolation structures. The deep trench isolation regions provide high electrical isolation where needed, while active pixel regions maintain appropriate electrical properties for sensing, allowing optimization of each region's local quality to address performance degradation
2Productivity
If pixel dimensions are reduced and pixel spacing is decreased to increase pixel density, then productivity and integration density are improved, but power consumption increases due to degraded performance
Solution Approach 1:
The deep trench isolation structures divide the substrate into electrically isolated pixel regions, reducing parasitic interactions and leakage currents between adjacent pixels. This segmentation lowers the overall power consumption of the pixel array while maintaining high pixel density, addressing the energy efficiency problem caused by scaling
Solution Approach 2:
The electrical parameters of the substrate are modified through selective doping and isolation techniques. By changing the electrical characteristics in different regions (high isolation in trench regions, appropriate conductivity in active regions), power consumption is reduced while maintaining the required pixel density and performance
3Reliability
If deep trench isolation structure is implemented to reduce short channel effects and noise, then device performance is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The deep trench isolation approach segments the substrate into discrete pixel regions separated by isolation trenches. While this creates structural complexity, it provides clear electrical isolation that directly improves device performance by reducing short channel effects and noise, making the complexity worthwhile for achieving the desired performance at scaled dimensions
Solution Approach 2:
The isolation structures extend vertically into the substrate, utilizing the depth dimension to achieve electrical isolation. This vertical dimensionality allows for effective isolation without proportionally increasing lateral complexity, as the deep trenches provide three-dimensional electrical barriers that improve performance while managing structural complexity
4Reliability
If deep trench isolation structure is implemented to reduce short channel effects and noise, then device performance is improved, but power consumption increases
Solution Approach 1:
The deep trench isolation structures create electrically isolated pixel regions that reduce parasitic leakage currents and improve signal integrity. This segmentation lowers the overall power consumption required to maintain the pixel array at high density, directly addressing the energy efficiency improvement while maintaining enhanced device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves device performance by reducing short channel effects and noise levels, allowing for larger pixel devices and lower power consumption, while also enhancing electrical and optical isolation between pixels.
Implementation Method 1
utilizing the DTI as an insulator to improve short channel effects and noise levels, thereby reducing power consumption
Implementation Method 2
An image sensor includes a pixel array (or grid) for detecting light and recording intensity (brightness) of the detected light. The pixel array responds to the light by accumulating a charge.
Data Source
AI summary
The present disclosure relates to a CMOS image sensor. The image sensor comprises a pixel region comprising a photodiode disposed within a substrate. A deep trench isolation (DTI) ring encloses the photodiode from top view and extends from a back-side to a first position within the substrate from cross-sectional view. A pair of shallow trench isolation (STI) structures is respectively disposed at an inner periphery and an outer periphery sandwiching the DTI ring from top view and extends from a front-side to a second position within the substrate from cross-sectional view. A pixel device is disposed at the front-side of the substrate directly overlying the DTI ring. The pixel device comprises a gate electrode disposed over the substrate and a pair of source/drain (S/D) regions disposed within the substrate and reaching on a top surface of the DTI ring.