Layered Pixel Power-Line Structure for Low-Capacitance Displays
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Solution Overview
Problem
Current display devices face challenges in efficiently managing power lines and data lines to minimize IR drop and parasitic capacitance, which affects the quality and resolution of the displayed images.
Innovation Solution
The display device incorporates a specific configuration with first and second power lines arranged in a layer different from the data lines, overlapping certain pixel circuits and data lines to act as shielding plates, and utilizing a planarization layer to connect pixel electrodes to thin film transistors through via holes, with the second via hole being larger than the first to facilitate easier connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Weight of moving object
If the display device is made thinner and lighter, then portability and modern design are improved, but IR drop and parasitic capacitance increase, degrading display performance
Solution Approach 1:
The patent transitions from planar power line arrangement to a three-dimensional stacked configuration. Power lines are arranged in multiple layers (first power line in first interlayer insulating layer, second power line in second interlayer insulating layer) with vertical connections via contact holes, effectively utilizing the Z-dimension to reduce parasitic capacitance while maintaining thin form factor.
Solution Approach 2:
The power distribution network is segmented into multiple independent power lines (first power line, second power line) operating at different voltage levels and located in different layers. This segmentation allows optimized routing for each power line, reducing overall IR drop and parasitic capacitance effects.
2Area of stationary object
If power lines are routed closer to data lines to reduce area, then device area is reduced, but parasitic capacitance between power and data lines increases
Solution Approach 1:
The patent resolves the area-capacitance tradeoff by moving the second power line to a higher layer (second interlayer insulating layer) above the data line layer. This vertical separation in the Z-dimension maintains compact planar area while significantly reducing parasitic capacitance between power and data lines.
Solution Approach 2:
The second interlayer insulating layer acts as an intermediary dielectric barrier between the second power line and the data line, reducing direct capacitive coupling while allowing close proximity routing for area efficiency.
3Power
If multiple power lines are added to improve power distribution, then power delivery is improved, but device complexity increases
Solution Approach 1:
The first and second power lines serve multiple functions: they provide different voltage levels for the thin film transistor (source and drain electrodes), act as electrostatic discharge protection paths, and function as part of the pixel circuit operation. This multi-functionality justifies the added complexity by consolidating multiple requirements into a unified power line structure.
Data Source
AI summary
There is provided a display device. The display device includes a first data line on a first interlayer insulating layer over a substrate, a first power line and a second power line on a second interlayer insulating layer, the second interlayer insulating layer covering the first data line, and a plurality of pixels. A first pixel among the plurality of pixels includes a display element including a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode, the second power line being connected to the opposite electrode, and a driving thin film transistor between the substrate and the display element and including a driving semiconductor layer, a driving gate electrode, a driving source electrode, and a driving drain electrode, the first interlayer insulating layer covering the driving gate electrode, and the first power line being connected to the driving source electrode.