Pixel Structure Parasitic Capacitance Elimination
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional pixel structures with a semiconductor-metal-insulator-ITO (SMII) storage capacitor suffer from parasitic capacitance issues due to exposed semiconductor layers, leading to defects like 'waterfall' and 'image sticking' in TFT-LCD displays, affecting display quality.
Innovation Solution
A pixel structure design that includes a substrate with a scan line, data line, TFT, semiconductor layer, metal capacitor electrode, passivation layer, pixel electrode, and transparent capacitor electrode, where the transparent capacitor electrode is positioned to minimize distance from the metal capacitor electrode and semiconductor layer, eliminating parasitic capacitance by ensuring a specific distance between these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source metal layer exposes a portion of the periphery of the semiconductor layer to form the SMII capacitor, then the storage capacitor can be formed, but parasitic capacitance is generated between the exposed semiconductor layer and the pixel electrode, causing display defects
Solution Approach 1:
The invention extracts and removes the harmful exposed semiconductor layer periphery from the capacitor structure. By defining the metal capacitor electrode's projection area to be completely within the semiconductor layer's projection area, the design eliminates the exposure of semiconductor layer edges, thereby removing the source of parasitic capacitance while preserving the storage capacitor functionality.
Solution Approach 2:
The invention applies local quality by creating a specific spatial relationship between the metal capacitor electrode and semiconductor layer. The metal electrode is positioned such that its projection area is entirely within the semiconductor layer's projection area, with a defined spacing from the edges. This localized positioning ensures that the capacitor function is maintained at the required location while avoiding parasitic capacitance generation at the periphery.
2Reliability
If the transparent capacitor electrode is positioned close to the metal capacitor electrode, then the capacitance value is improved, but the risk of short circuit and parasitic capacitance increases
Solution Approach 1:
The invention introduces the passivation layer as an intermediary between the metal capacitor electrode and the transparent capacitor electrode. The passivation layer covers both electrodes and provides electrical isolation, allowing them to be positioned close together for optimal capacitance while preventing short circuits and parasitic capacitance through the insulating barrier it provides.
Solution Approach 2:
The invention applies local quality by creating a specific spatial arrangement where the transparent capacitor electrode's projection area is within the metal capacitor electrode's projection area, with a controlled minimum distance (0-6 micrometers) between their edges. This localized positioning optimizes capacitance while the passivation layer ensures electrical isolation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance, stabilizes electrical performance, and enhances display quality by preventing defects such as 'waterfall' and 'image sticking', ensuring consistent performance across various operational states.
Implementation Method 1
The passivation layer is configured on the substrate and covers the scan line, the data line, the TFT, the metal capacitor electrode, and the semiconductor layer
Implementation Method 2
a storage capacitor is configured in a pixel structure... the metal capacitor electrode is configured on the semiconductor layer... the transparent capacitor electrode is configured on the passivation layer
Data Source
AI summary
A pixel structure having an SMII (semiconductor-metal-insulator-ITO) capacitor is provided. Specifically, a partial region of a transparent electrode layer corresponding to a semiconductor layer is removed, so as to eliminate parasitic capacitance between the transparent electrode layer and the semiconductor layer, prevent defects (e.g., waterfall, image sticking, etc.) from occurring on the display frame, and improve the display quality.