Planar IC Package Structure for Reduced Thermal Warpage
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Solution Overview
Problem
Conventional integrated circuit (IC) packages face challenges in achieving smaller form factors due to thermal warpage issues and limited performance and reliability, particularly in next-generation computing devices, where reducing substrate thickness is difficult and wire bonding techniques are less effective compared to flip chip architectures.
Innovation Solution
The development of IC package structures with a single metal layer and a single dielectric layer, utilizing a 'solder on die' or 'solder on package' technique, which eliminates the need for via drilling and allows for smaller form factors, reduced material and manufacturing costs, and increased contact density, while maintaining high-frequency signaling capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional IC packages use multiple metal and dielectric layers with vertical vias, then electrical signal routing capability is improved, but substrate thickness cannot be reduced and manufacturing complexity increases
Solution Approach 1:
The patent extracts and eliminates the via structures from the substrate. Instead of having vertical vias penetrating through multiple dielectric layers to connect metal layers, the invention uses a planar metal layer where all electrical connections are made through conductive elements in the same plane, connected by conductive traces. This extraction of the via component simplifies the substrate structure while maintaining electrical routing capability.
Solution Approach 2:
The patent transitions from a three-dimensional vertical routing architecture (multiple metal layers connected by vertical vias) to a two-dimensional planar routing architecture (single metal layer with horizontal traces). By changing the dimensionality of signal routing from vertical to lateral, the substrate can be made thinner while maintaining electrical connection capabilities.
2Volume of moving object
If substrate thickness is reduced to achieve smaller form factor, then form factor is improved, but thermal warpage issues worsen
Solution Approach 1:
The patent removes the via structures that extend through the substrate thickness, eliminating the source of thermal warpage. By using a planar metal layer without vertical vias, the substrate can be made thinner without the thermal stress concentrations that cause warpage in conventional multi-layer substrates with through-vias.
Solution Approach 2:
The patent changes the structural parameters of the substrate by using a single dielectric layer with a planar metal layer, eliminating the multi-layer stacked structure. This parameter change allows for reduced substrate thickness while maintaining thermal stability, as the simplified structure has fewer interfaces and less accumulated thermal stress.
3Ease of manufacture
If wire bonding technique is used instead of flip chip, then ease of manufacture is improved, but performance and reliability worsen
Solution Approach 1:
The patent enables the substrate to provide its own electrical connection functionality through the planar metal layer with integrated conductive traces and elements. The substrate structure itself serves as the interconnection medium, eliminating the need for separate wire bonding or flip chip processes, thereby achieving both ease of manufacture and high reliability.
4Reliability
If multiple metal layers are used, then electrical signal routing capability is improved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent extracts and removes the multiple metal layers and vertical via structures, replacing them with a single planar metal layer. The electrical routing function is maintained through conductive traces patterned in the planar metal layer, eliminating the need for multiple stacked metal layers and their associated manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the creation of low-cost, low-complexity IC packages with smaller form factors, suitable for mobile and networking devices, providing increased computing power and improved manufacturing efficiency by reducing the need for complex tool sets and minimizing thermal warpage issues.
Implementation Method 1
package solder material disposed on the metal layer such that the package solder material is electrically coupled to the die via the metal layer
Data Source
AI summary
Integrated circuit (IC) package structures, and related devices and methods, are disclosed herein. In some embodiments, an IC package substrate may include: a dielectric layer having a first face and a second face; a metal layer disposed at the first face of the dielectric layer and having a first face and a second face, wherein the second face of the metal layer is disposed between the first face of the metal layer and the second face of the dielectric layer; a package contact at the first face of the metal layer to couple the IC package substrate to a component; and a die contact at the first face of the metal layer to couple a die to the IC package substrate.