Planar Power MOS Transistor with Trench Gate for CMOS Integration
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Solution Overview
Problem
Power MOS transistors face challenges in maintaining high breakdown voltage and high current output while being compact enough for integration with CMOS-processed chips, as vertical structures like VDMOS and UMOS transistors suffer from increased resistance when scaled down and cannot be integrated with logic circuits.
Innovation Solution
A planar-structured power MOS transistor with a trench gate and asymmetric insulating layer, featuring a drain region, source region, well region, deep well region, and substrate region, which allows for lateral connection and reduced resistance, enabling high breakdown voltage and current output without the need for epitaxial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If vertical structure (VDMOS or UMOS) is used to achieve high breakdown voltage and high current output, then power output capability is improved, but device size increases and integration with CMOS circuits becomes difficult
Solution Approach 1:
The patent transitions from vertical current flow (VDMOS) to lateral current flow through the channel, enabling planar integration while maintaining power capability. The trench gate structure creates a lateral field effect transistor configuration where current flows horizontally between source and drain regions, allowing compact 2D layout suitable for CMOS integration.
Solution Approach 2:
The trench gate is formed by etching a trench into the semiconductor substrate and filling it with conductive material, creating a nested structure where the gate is embedded within the substrate. This nested configuration achieves high voltage capability without increasing lateral device footprint, as the gate structure extends vertically into the substrate rather than laterally.
2Area of stationary object
If UMOS transistor with epitaxial layer is scaled down to reduce size, then device area is reduced, but resistance of epitaxial layer increases offsetting current gain
Solution Approach 1:
The patent employs selective doping with different conductivity types in different regions: n-type source and drain regions, p-type well region, and n-type substrate. This local quality variation creates optimized electrical characteristics in each region, reducing overall resistance while maintaining high breakdown voltage. The asymmetric insulating layer also provides local quality enhancement at the gate interface.
Solution Approach 2:
The insulating layer surrounding the trench gate is designed with asymmetric thickness, being thicker on one side than the other. This asymmetric configuration optimizes the electric field distribution, reducing resistance in high-current paths while maintaining high breakdown voltage, thereby resolving the contradiction between size reduction and resistance increase.
3Power
If multiple power MOS transistor cells are combined to increase current output, then current capability is improved, but device size increases making it unacceptable for manufacturing
Solution Approach 1:
The power MOS transistor is segmented into distinct functional regions (source region, drain region, well region, substrate region) with optimized doping profiles. This segmentation allows each region to contribute efficiently to current conduction, achieving high current output from a single compact cell rather than requiring multiple cells to be combined.
Solution Approach 2:
The patent utilizes controlled doping concentration parameters in different regions to optimize electrical characteristics. By adjusting doping levels in source, drain, and well regions, the transistor achieves high current capability intrinsically within a single cell structure, eliminating the need to combine multiple cells and thereby reducing overall device size.
Data Source
AI summary
An integrated circuit includes a power MOS transistor which comprises a drain region, a trench gate, a source region, a well region, a deep well region and a substrate region. The drain region has a doping region of a first conductivity type connected to a drain electrode. The trench gate has an insulating layer and extends into the drain region. The source region has a doping region of the first conductivity type connected to a source electrode. The well region is doped with a second conductivity type, formed under the source region, and connected to the source electrode. The deep well region is doped with the first conductivity type and is formed under the drain region and the well region. The substrate region is doped with the second conductivity type and is formed under the deep well region. The drain region is formed at one side of the trench gate and the source region is formed at the opposing side of the trench gate such that the trench gate laterally connects the source region and the drain region.