Scalable Planar Phased Array Antenna Tile Assembly
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Solution Overview
Problem
Conventional phased array antenna systems are complex, costly, and less adaptable due to their large size and high part counts, leading to higher manufacturing costs and lower yields, making them expensive and less efficient for high-fidelity performance.
Innovation Solution
A scalable subarray tile assembly using an antenna integrated printed wiring board (AiPWB) with thin pre-pegs/copper layers and laser-drilled microvias for direct connection to high-density integrated circuit die, combined with plated through vias for thermal and mechanical stress relief, and a metallic honeycomb structure with dielectric-filled waveguides, reduces parts count and assembly complexity while maintaining high performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If larger array tile assemblies are used to integrate more functionality, then high fidelity phased array antenna performance is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent divides the phased array antenna system into modular subarray tile assemblies, each containing a manageable number of antenna elements (e.g., 16 elements) and integrated circuit die. These modules can be independently manufactured, tested, and assembled, reducing the complexity of individual tiles while maintaining overall system performance through modular scaling.
Solution Approach 2:
The patent transitions from planar two-dimensional array configurations to three-dimensional integrated structures by stacking multiple circuit layers (substrate layers, intermediate layers, and antenna element layers) vertically. This vertical integration reduces the horizontal footprint and allows more functionality to be packed into each modular tile without proportionally increasing complexity.
2Reliability
If larger array tile assemblies are used to integrate more functionality, then high fidelity phased array antenna performance is achieved, but manufacturing cost increases
Solution Approach 1:
By segmenting the system into standardized modular tiles, the patent enables parallel manufacturing of multiple identical units, improving manufacturing efficiency and reducing per-unit costs. Each module can be produced using the same fabrication processes, allowing for economies of scale and simplified supply chain management.
Solution Approach 2:
The patent designs universal substrate layers and intermediate layers that can be used across different tile configurations and array sizes. These standardized components with consistent material properties and geometric patterns can be manufactured using the same processes regardless of the final array configuration, reducing tooling costs and manufacturing complexity.
3Adaptability or versatility
If conventional printed wiring boards with multiple laminations are used, then functionality is integrated, but via-aspect ratios increase and manufacturing yield decreases
Solution Approach 1:
The patent applies different layer thicknesses and via configurations in different regions of the printed wiring board. Critical signal paths use optimized via dimensions and local impedance control, while non-critical areas use standard configurations. This localized optimization maintains signal integrity without requiring uniformly thick layers throughout the entire board, improving manufacturing yield.
Solution Approach 2:
The patent optimizes via aspect ratios by adjusting via diameter, depth, and plating thickness parameters based on local requirements. By changing these geometric parameters rather than using a fixed via design throughout the board, the patent achieves reliable electrical connections while maintaining manufacturability and higher production yields.
Data Source
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AI summary
Systems and methods according to one or more examples are provided for a scalable planar phased array antenna subarray tile assembly. A scalable phased array antenna subarray tile assembly is implemented as a printed wiring board (PWB) with antenna elements coupled to the PWB. In one example, a PWB includes integrated circuit die attached directly to a first surface of the PWB and couple to antenna elements coupled on a second surface of the PWB. First conductive vias extend through a first subset of PWB layers and couple to the integrated circuit die. Second conductive vias, larger than the first, extend through a second subset of PWB layers and couple to the antenna elements. A conductive trace couples the first and second conductive vias on a PWB layer. The second conductive vias are offset from the first to provide a thermal mechanical stress relief to the integrated circuit die.